3D semiconductor devices and structures with slits
A semiconductor device including: a first level including memory control circuits (include a plurality of refresh circuits for the memory units) which include first transistors; a second level including a first array of memory cells including second transistors self-aligned to at least one of the third transistors; a third level disposed on top of the second level disposed on top of first level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, second level is bonded to the first level, a plurality of slits disposed through the second level, the third level, and the fourth level, the slits enable gate replacement of a plurality of the third transistors, where the second array of memory cells include a plurality of independently controlled memory units.
1 . A semiconductor device, the device comprising:
a first level comprising memory control circuits, said memory control circuits comprising first transistors;
a second level disposed on top of said first level, said second level comprising a first array of memory cells comprising second transistors;
a third level disposed on top of said second level, said third level comprising a second array of memory cells comprising third transistors;
a fourth level disposed on top of said third level, said fourth level comprising a third array of memory cells comprising fourth transistors,
wherein said second level is bonded to said first level,
wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following a same lithography step; and
a plurality of slits disposed through said second level, said third level, and said fourth level,
wherein said slits enable gate replacement of a plurality of said third transistors,
wherein said second array of memory cells comprise a plurality of independently controlled memory units, and
wherein said memory control circuits comprise a plurality of refresh circuits for said memory units.
2 . The device according to claim 1 ,
wherein said memory control circuits comprise cache memory.
3 . The device according to claim 1 , further comprising:
a plurality of redundancy memory cells.
4 . The device according to claim 1 ,
wherein said memory cells each comprise a charge trap layer.
5 . The device according to claim 1 ,
wherein at least one of said second transistors comprises a polysilicon transistor channel.
6 . The device according to claim 1 , further comprising:
a plurality of One Time Programmable (“OTP”) fuses.
7 . The device according to claim 1 , further comprising:
a fifth level disposed on top of said fourth level,
wherein said fifth level comprises single crystal silicon.
8 . A semiconductor device, the device comprising:
a first level comprising memory control circuits, said memory control circuits comprising first transistors;
a second level disposed on top of said first level, said second level comprising a first array of memory cells comprising second transistors;
a third level disposed on top of said second level, said third level comprising a second array of memory cells comprising third transistors;
a fourth level disposed on top of said third level, said fourth level comprising a third array of memory cells comprising fourth transistors,
wherein said second level is bonded to said first level,
wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following a same lithography step; and
a plurality of slits disposed through said second level, said third level, and said fourth level,
wherein said slits enable gate replacement of a plurality of said third transistors,
wherein said second array of memory cells comprise a plurality of independently controlled memory units, and
wherein said memory control circuits comprise cache memory.
9 . The device according to claim 8 ,
wherein said memory control circuits comprise a plurality of refresh circuits for said memory units.
10 . The device according to claim 8 ,
wherein said plurality of independently controlled memory units comprises at least four memory units.
11 . The device according to claim 8 ,
wherein said memory cells each comprise a charge trap layer.
12 . The device according to claim 8 ,
wherein at least one of said second transistors comprises a polysilicon transistor channel.
13 . The device according to claim 8 , further comprising:
a plurality of One Time Programmable (“OTP”) fuses.
14 . The device according to claim 8 , further comprising:
a fifth level disposed on top of said fourth level,
wherein said fifth level comprises single crystal silicon.
15 . A semiconductor device, the device comprising:
a first level comprising memory control circuits, said first level comprising first transistors;
a second level disposed on top of said first level, said second level comprising a first array of memory cells comprising second transistors;
a third level disposed on top of said second level, said third level comprising a second array of memory cells comprising third transistors;
a fourth level disposed on top of said third level, said fourth level comprising a third array of memory cells comprising fourth transistors,
wherein said second level is bonded to said first level,
wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following a same lithography step;
a plurality of slits disposed through said second level, said third level, and said fourth level,
wherein said slits enable gate replacement of a plurality of said third transistors,
wherein said second array of memory cells comprise a plurality of independently controlled memory units; and
a plurality of redundancy memory cells,
wherein said memory control circuits comprise a plurality of refresh circuits for said memory units.
16 . The device according to claim 15 ,
wherein said memory control circuits comprise cache memory.
17 . The device according to claim 15 ,
wherein said memory cells each comprise a charge trap layer.
18 . The device according to claim 15 ,
wherein at least one of said second transistors comprise a polysilicon transistor channel.
19 . The device according to claim 15 , further comprising:
a plurality of One Time Programmable (“OTP”) fuses.
20 . The device according to claim 15 , further comprising:
a fifth level disposed on top of said fourth level,
wherein said fifth level comprises single crystal silicon.