Wafer level packaging process for thin film inductors
An aspect relates to a method of forming an integrated circuit (IC) package, including: forming a thin-film inductor (TFI) over a first dummy carrier wafer; attaching an integrated circuit (IC) die to and over the TFI; attaching a second dummy carrier wafer to and over the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to and under the TFI; and removing the second dummy carrier wafer from the IC die. Another aspect relates to a method of forming an IC package, including forming a first redistribution layer (RDL) over a through-silicon via (TSV); forming a second RDL under the TSV; forming a thin-film inductor (TFI) over the first RDL; and attaching at least one integrated circuit (IC) die to the second RDL or the TFI.
1 . A method of forming an integrated circuit (IC) package, comprising:
forming a thin-film inductor (TFI) over a first dummy carrier wafer comprising:
forming a first magnetic layer over a first electrical insulating layer;
forming a first redistribution layer (RDL) over the first magnetic layer;
forming an electrical insulating dome over the first RDL; and
forming a second magnetic layer over the electrical insulating dome;
attaching an integrated circuit (IC) die to and over the TFI;
attaching a second dummy carrier wafer to and over the IC die;
removing the first dummy carrier wafer from the TFI;
attaching at least one solder bump to and under the TFI; and
removing the second dummy carrier wafer from the IC die.
2 . The method of claim 1 , further comprising:
forming a first bonding layer over the first dummy carrier wafer; and
forming the first electrical insulating layer over the first bonding layer.
3 . The method of claim 2 , further comprising forming a metallized via hole into the first electrical insulating layer, wherein the first RDL is electrically coupled to the metallized via hole.
4 . The method of claim 2 , further comprising:
forming a first passivation layer over the first RDL;
forming a metallized via hole through the first passivation layer; and
forming a second RDL over the first passivation layer and the metallized via hole, wherein the second RDL is electrically coupled to the first RDL by way of the metallized via hole.
5 . The method of claim 4 , further comprising:
forming a second passivation layer over the second RDL;
forming an under bump metal (UBM) through the second passivation layer and over the second RDL; and
forming a solder bump over the UBM, wherein the solder bump is electrically coupled to the first RDL via the UBM, second RDL, and the metallized via hole.
6 . The method of claim 1 , wherein attaching the second dummy carrier wafer to and over the IC die, comprises:
forming a bonding layer over the IC die; and
placing the second dummy carrier wafer over the bonding layer.
7 . The method of claim 6 , wherein the second dummy carrier wafer comprises a transparent material, and wherein removing the second dummy carrier wafer from the IC die comprises subjecting the bonding layer to a laser via the second dummy carrier wafer to debond the bonding layer from the IC die.
8 . The method of claim 1 , wherein the TFI is attached to the first dummy carrier wafer by way of a bonding layer, wherein the first dummy carrier wafer comprises a transparent material, and wherein removing the first dummy carrier wafer from the TFI comprises subjecting the bonding layer to a laser via the first dummy carrier wafer to debond the bonding layer from the TFI.
9 . The method of claim 1 , wherein the TFI comprises a set of TFIs, wherein the IC die comprises a set of IC dies electrically coupled to the set of TFIs, respectively, and further comprising dicing the IC package to separate distinct pairs of TFI and IC dies.
10 . The method of claim 1 , wherein the TFI comprises a set of TFIs, wherein the IC die comprises sets of distinct IC dies, wherein at least one of the sets of distinct IC dies is electrically coupled to the set of TFIs, respectively, and further comprising dicing the IC package to separate distinct pairs of TFI and set of distinct IC dies.
11 . An integrated circuit (IC) package, comprising:
at least one thin-film inductor (TFI), comprising:
a first magnetic layer;
a first redistribution layer (RDL) situated over and electrically isolated from the first magnetic layer, wherein first and second portions of the first RDL on opposite sides of the first magnetic layer serve as the first and second terminals of the at least one TFI, respectively;
an electrical insulating dome situated over the first RDL and the first magnetic layer; and
a second magnetic layer situated over the electrical insulating dome, wherein the electrical insulating dome electrically isolates the second magnetic layer from the first RDL;
a set of integrated circuit (IC) dies coupled to the at least one TFI; and
a set of solder bump coupled to the at least one TFI.
12 . The IC package of claim 11 , wherein at least one of the set of IC dies include an aluminum (AP) layer coupled to a first terminal of the at least one TFI.
13 . The IC package of claim 11 , wherein at least one of the set of solder bump is coupled to a second terminal of the at least one TFI.
14 . The IC package of claim 13 , wherein the at least one of the set of solder bump is coupled to the second terminal of the TFI by way of an under bump metal (UBM), a second redistribution layer (RDL), and a metallized via hole through a passivation layer.
15 . A method of forming an integrated circuit (IC) package, comprising:
forming a first redistribution layer (RDL) over a through-silicon via (TSV);
forming a second RDL under the TSV;
forming a thin-film inductor (TFI) over the first RDL; and
attaching at least one integrated circuit (IC) die to the second RDL or the TFI.
16 . The method of claim 15 , wherein forming the TFI over the first RDL, comprises:
forming an electrical insulating layer over the first RDL;
forming a first magnetic layer over the electrical insulating layer;
forming a third redistribution layer (RDL) over the first magnetic layer;
forming an electrical insulating dome over the third RDL; and
forming a second magnetic layer over the electrical insulating dome.
17 . The method of claim 16 , wherein the electrical insulating dome comprises a polymer.
18 . The method of claim 16 , further comprising forming a metallized via hole into the electrical insulating layer, wherein the first and third RDLs are electrically coupled to the metallized via hole.
19 . The method of claim 16 , further comprising:
forming a first passivation layer over the third RDL;
forming a metallized via hole through the first passivation layer; and
forming a fourth RDL over the first passivation layer and the metallized via hole, wherein the fourth RDL is electrically coupled to the third RDL by way of the metallized via hole.
20 . The method of claim 1 , further comprising:
forming a second passivation layer over the fourth RDL;
forming an under bump metal (UBM) through the second passivation layer and over the fourth RDL; and
forming a solder bump over the UBM, wherein the solder bump is electrically coupled to the third RDL via the UBM, fourth RDL, and the metallized via hole.
21 . The method of claim 20 , wherein attaching the at least one IC die to the TFI comprises attaching the at least one IC die to the fourth RDL.
22 . An integrated circuit (IC) package, comprising:
a thin-film inductor (TFI), comprising:
a first magnetic layer;
a first redistribution layer (RDL) situated over and electrically isolated from the first magnetic layer, wherein first and second portions of the first RDL on opposite sides of the first magnetic layer serve as the first and second terminals of the at least one TFI, respectively;
an electrical insulating dome situated over the first RDL and the first magnetic layer; and
a second magnetic layer situated over the electrical insulating dome, wherein the electrical insulating dome electrically isolates the second magnetic layer from the first RDL;
an integrated circuit (IC) die coupled to a first terminal of the TFI;
a solder bump coupled to a second terminal of the TFI; and
a through-silicon via (TSV) by way of which the IC die or the solder bump is coupled to the first terminal or the second terminal of the TFI, respectively.
23 . The IC package of claim 22 , wherein the IC die is coupled to the first terminal of the TFI by way of the TSV.
24 . The IC package of claim 23 , wherein the IC die is coupled to the first terminal of the TFI further by way of the first RDL.
25 . The IC package of claim 24 , wherein the solder bump is coupled to the second terminal of the TFI by way of the second RDL.
26 . The IC package of claim 22 , wherein the solder bump is coupled to the second terminal of the TFI by way of the TSV.
27 . The IC package of claim 26 , wherein the solder bump is coupled to the second terminal of the TFI further by way of the first RDL.
28 . The IC package of claim 27 , wherein the IC is coupled to the first terminal of the TFI by way of the second RDL.