IP Library Granted Patent US 12,489,037
Granted Patent B2
US 12,489,037 · App. 18/104,278 · Granted Dec 2, 2025

Semiconductor package substrate with a smooth groove straddling topside and sidewall

Inventors: Bob Lee (New Taipei, TW); Kim Hong Lucas Chai (Dresden, DE)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H01L23/49541H01L21/56H01L23/3107H01L23/49513H01L23/49582H01L24/32H01L24/48H01L24/73H01L24/83H01L24/85H01L24/92H01L2224/26175H01L2224/32245H01L2224/48245H01L2224/48465H01L2224/73265H01L2224/83855H01L2224/858H01L2224/92247
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Quick Facts
Patent No.
US 12,489,037
App. No.
18/104,278
Granted
Dec 2, 2025
Kind
B2
Abstract

A semiconductor package includes a metallic substrate, the metallic substrate including a roughened surface, a semiconductor die including bond pads, and an adhesive between the roughened surface of a topside of the metallic substrate and the semiconductor die, therein bonding the semiconductor die to the metallic substrate. The adhesive includes a resin. The metallic substrate further includes a groove about a perimeter of the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic substrate. The groove straddles the topside and a sidewall of the metallic substrate.

Claims (26)

1 . A semiconductor package comprising:

a metallic substrate, the metallic substrate including a roughened surface;

a semiconductor die including bond pads; and

an adhesive between the roughened surface of a topside of the metallic substrate and the semiconductor die, therein bonding the semiconductor die to the metallic substrate, wherein the adhesive includes a resin,

wherein the metallic substrate further includes a groove about a perimeter of the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic substrate,

wherein the groove straddles the topside and a sidewall of the metallic substrate.

2 . The semiconductor package of claim 1 , wherein the semiconductor die is a first semiconductor die, the adhesive is a first adhesive, and the groove is a first groove, the package further comprising a second semiconductor die bonded to the topside of the metallic substrate by a second adhesive, wherein the metallic substrate further includes a second groove about a perimeter of the second semiconductor die on the roughened surface, with the first adhesive separated from the second adhesive by a portion of the metallic substrate between the first groove and the second groove.

3 . The semiconductor package of claim 1 , wherein the groove is configured to prevent the resin of the adhesive from bleeding onto the roughened surface of the metallic substrate outside the groove.

4 . The semiconductor package of claim 1 , wherein a resin bleed of the adhesive is adjacent to at least a portion of the groove.

5 . The semiconductor package of claim 1 , wherein the adhesive is adjacent to at least a portion of the groove.

6 . The semiconductor package of claim 1 , wherein the groove forms a rectangular shape about the semiconductor die on the roughened surface.

7 . The semiconductor package of claim 1 , wherein all surfaces of the metallic substrate are roughened except for the groove.

8 . The semiconductor package of claim 1 ,

wherein a surface roughness of the metallic substrate is at least 1.0 micrometers (μm), and

wherein a surface roughness of the groove is less than 0.5 micrometers (μm).

9 . The semiconductor package of claim 1 , wherein a side of the metallic substrate including the roughened surface includes one or more of a group consisting of:

a metal oxide layer;

a micro-crystalline metal layer; and

a rough nickel layer.

10 . The semiconductor package of claim 1 , wherein the metallic substrate includes a metallic pad adjacent to the semiconductor die and a pad lead integral with and extending from the metallic pad, wherein the groove straddles the topside and the sidewall of the pad lead of the metallic substrate.

11 . The semiconductor package of claim 10 , further comprising a wire bond extending between one of the bond pads of the semiconductor die and the pad lead.

12 . The semiconductor package of claim 11 , further comprising:

additional leads spaced from the metallic pad by a gap; and

additional wire bonds extending between the bond pads of the semiconductor die and the additional leads spaced from the metallic pad by the gap.

13 . The semiconductor package of claim 12 , wherein the semiconductor die is a first semiconductor die, the adhesive is a first adhesive, and the groove is a first groove, the package further comprising a second semiconductor die bonded to the topside of the metallic substrate by a second adhesive, wherein the metallic substrate further includes a second groove about a perimeter of the second semiconductor die on the roughened surface, with the first adhesive separated from the second adhesive by a portion of the metallic substrate between the first groove and the second groove.

14 . The semiconductor package of claim 12 , further comprising mold compound covering the semiconductor die, the adhesive, the roughened surface of the metallic substrate, and at least partially covering the pad lead and the additional leads.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2023
From: LEE, BOB; LUCAS CHAI, KIM HONG
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 062565/0195 →
Continuity (1)
Related Publication 20240258210A1 · Aug 1, 2024
References Cited (16)
US 6828660B2 · Abbott · 2004 [cited by applicant]
US 7183657B2 · Furtaw et al. · 2007 [cited by applicant]
US 7358617B2 · Cruz et al. · 2008 [cited by applicant]
US 8044495B2 · Abbott · 2011 [cited by applicant]
US 8158460B2 · Abbott · 2012 [cited by applicant]
US 8587099B1 · Abbott · 2013 [cited by applicant]
US 9054092B2 · Gallegos et al. · 2015 [cited by applicant]
US 20070269930A1 · Gupta et al. · 2007 [cited by applicant]
US 20130025745A1 · Abbott et al. · 2013 [cited by applicant]
US 20130154117A1 · Tan et al. · 2013 [cited by applicant]
US 20180166420A1 · Park et al. · 2018 [cited by applicant]
US 20190074431A1 · Hasegawa et al. · 2019 [cited by applicant]
US 20190311974A1 · Hashizume · 2019 [cited by examiner]
US 20200273813A1 · Wee et al. · 2020 [cited by applicant]
US 20210193590A1 · Wang · 2021 [cited by examiner]
US 20230017286A1 · Zhang et al. · 2023 [cited by applicant]