Resistive random access memory based one-time-programmable memory devices
View Patent ↗A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.
1 . A memory device, comprising:
a first memory array including a plurality of first memory bits, each of the plurality of first memory bits being configured as a one-time-programmable (OTP) memory bit;
a second memory array including a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit; and
a lock bit circuit operatively coupled to the first memory array;
wherein the lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.
2 . The memory device of claim 1 , wherein the plurality of first memory bits and the plurality of second memory bits are each a resistive random access memory (RRAM) bit.
3 . The memory device of claim 1 , wherein the lock bit has (i) a high logic state indicating that the at least one first memory bit has been programmed; and (ii) a low logic state indicating that the at least one first memory bit has not been programmed.
4 . The memory device of claim 1 , wherein each of the plurality of first memory bits has a first variable resistance that is formed with a first resistance and configured to be programmed to a second resistance, the second resistance being lower than the first resistance.
5 . The memory device of claim 4 , wherein the lock bit circuit comprises an AND gate having a first input and a second input, the first input being configured to sense a voltage presented by the at least one first memory bit, the second input being configured to receive a control signal.
6 . The memory device of claim 5 , wherein the voltage is determined based on whether the at least one first memory bit has the first resistance or the second resistance.
7 . A memory device, comprising:
a first memory array including a plurality of first memory bits, each of the plurality of first memory bits comprising a first access transistor and a first resistor coupled in series, the first resistor having a first variable resistance; and
a lock bit circuit operatively coupled to the first memory array;
wherein the lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been permanently programmed from a first resistance to a second resistance, the second resistance being lower than the first resistance.
8 . The memory device of claim 7 , wherein the lock bit circuit comprises:
a reference resistor having a fixed resistance;
a reference transistor connected to the reference resistor in series;
a first clamping transistor;
a second clamping transistor; and
an AND gate.
9 . The memory device of claim 8 , wherein the fixed resistance is higher than the second resistance but lower than the first resistance.
10 . The memory device of claim 8 , wherein the reference transistor and the first access transistor are cross-coupled to each other.
11 . The memory device of claim 8 , wherein when the lock bit circuit is in a program mode, the lock bit circuit is configured to provide a conduction path flowing through the first resistor to the first access transistor and one of the first or second clamping transistor.
12 . The memory device of claim 8 , wherein when the lock bit circuit is in a read mode, the lock bit circuit is configured to compare the first resistor with the reference resistor so as to determine a voltage at a node connected between the first resistor and the first access transistor, the node being connected to one of two inputs of the AND gate.
13 . The memory device of claim 12 , wherein when the first resistor has been permanently programmed to have the second resistance, the voltage at the node is at a high logic state.
14 . The memory device of claim 13 , wherein when the first resistor remains with the first resistance, the voltage at the node is at a low logic state.
15 . The memory device of claim 14 , wherein the lock bit circuit is configured to generate the lock bit based on the voltage at the node.
16 . The memory device of claim 7 , further comprising:
a second memory array including a plurality of second memory bits, each of the plurality of second memory bits comprising a second access transistor and a second resistor coupled in series, the second resistor having a second variable resistance;
wherein the lock bit circuit is not operatively coupled to the second memory array.
17 . The memory device of claim 16 , wherein each of the plurality of second memory bits is configured to be reversibly programmed between the first resistance and the second resistance.
18 . A method for operating a memory device, comprising:
providing a memory array including a plurality of resistive random access memory (RRAM) bits;
permanently programming at least one of the plurality of RRAM bits based on changing a resistance of the at least one RRAM bit;
comparing the resistance of the at least one RRAM bit with a reference resistance; and
generating, based on the comparison, a lock bit indicating whether the at least one RRAM bit has been permanently programmed.
19 . The method of claim 18 , further comprising:
in response to determining that the resistance is greater than the reference resistance, generating the lock bit with a first logic state indicating that the at least one RRAM bit has not been permanently programmed.
20 . The method of claim 18 , further comprising:
in response to determining that the resistance is lower than the reference resistance, generating the lock bit with a second logic state indicating that the at least one RRAM bit has been permanently programmed.