IP Library › Granted Patent US 12,494,456
Granted Patent B2
US 12,494,456 · App. 17/940,021 · Granted Dec 9, 2025

Semiconductor assembly and method for manufacturing the same

Inventors: Kun-Ju Li (Tainan, TW); Hsin-Jung Liu (Pingtung County, TW); Zong-Sian Wu (Tainan, TW); Wei-Xin Gao (Tainan, TW); Jhih-Yuan Chen (Kaohsiung, TW); Ang Chan (Taipei, TW); Chau-Chung Hou (Tainan, TW); Hsiang-Chi Chien (Pingtung County, TW); I-Ming Lai (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP
H01L25/0657H01L24/05H01L24/06H01L24/08H01L24/80H10D84/0156H10D84/0191H10D84/038H01L2224/05018H01L2224/05073H01L2224/05157H01L2224/05166H01L2224/05176H01L2224/05181H01L2224/05187H01L2224/05541H01L2224/05576H01L2224/05624H01L2224/05647H01L2224/05687H01L2224/0603H01L2224/08145H01L2224/80895H01L2224/80896H01L2225/06524H01L2225/06527H01L2225/06544
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Quick Facts
Patent No.
US 12,494,456
App. No.
17/940,021
Granted
Dec 9, 2025
Kind
B2
Abstract

A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.

Claims (23)

1 . A semiconductor assembly, comprising:

a first substrate;

a first well in the first substrate and having a first doping type;

a second substrate;

a second well in the second substrate and having a second doping type different from the first doping type;

a first dielectric layer between the first substrate and the second substrate;

a second dielectric layer between the first substrate and the second substrate;

a third well in the first substrate and having the second doping type; and

a fourth well in the second substrate and having the first doping type,

wherein the second dielectric layer is bonded to the first dielectric layer, the first well overlaps with the second well in a longitudinal direction, and the third well overlaps with the fourth well in the longitudinal direction.

2 . The semiconductor assembly according to claim 1 , further comprising a first via element in the first dielectric layer and a second via element in the second dielectric layer, wherein the first via element is bonded to the second via element, the first well, the second well, the first via element and the second via element are electrically connected to each other.

3 . The semiconductor assembly according to claim 2 , further comprising:

a first doping region in the first well and having the first doping type; and

a second doping region in the second well and having the second doping type,

wherein the first via element is electrically connected to the first doping region in the first well, the second via element is electrically connected to the second doping region in the second well.

4 . The semiconductor assembly according to claim 2 , further comprising a first conductive region in the first dielectric layer and between the first via element and the first substrate.

5 . The semiconductor assembly according to claim 2 , further comprising a second conductive region in the second dielectric layer and between the second via element and the second substrate, wherein an area of the second conductive region is larger than an area of the second via element.

6 . The semiconductor assembly according to claim 1 , wherein the third well adjoins the first well, the fourth well adjoins the second well.

7 . The semiconductor assembly according to claim 1 , further comprising:

a third doping region in the third well and having the second doping type; and

a fourth doping region in the fourth well and having the first doping type.

8 . The semiconductor assembly according to claim 7 , further comprising a third via element and a fourth via element, wherein the third via element is in the first dielectric layer and electrically connected to the third doping region in the third well, the fourth via element is in the second dielectric layer and electrically connected to the fourth doping region in the fourth well, the third via element is bonded to the fourth via element.

9 . The semiconductor assembly according to claim 8 , further comprising a third conductive region in the first dielectric layer and between the third via element and the first substrate, the third via element, the third conductive region and the third doping region in the third well are electrically connected to each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2022
From: LI, KUN-JU; LIU, HSIN-JUNG; WU, ZONG-SIAN; GAO, WEI-XIN; CHEN, JHIH-YUAN; CHAN, ANG; HOU, CHAU-CHUNG; CHIEN, HSIANG-CHI; LAI, I-MING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 061020/0781 →
Priority Claims (1)
TW 111130044 · Aug 10, 2022 · national
Continuity (1)
Related Publication 20240055401A1 · Feb 15, 2024
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