IP Library › Granted Patent US 12,495,222
Granted Patent B2
US 12,495,222 · App. 18/357,045 · Granted Dec 9, 2025

Solid-state imaging device and method of controlling solid-state imaging device

Inventors: Taiichiro Watanabe (Kanagawa, JP); Tetsuji Yamaguchi (Kanagawa, JP); Yusuke Sato (Kanagawa, JP); Fumihiko Koga (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N25/626H10K39/32
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Quick Facts
Patent No.
US 12,495,222
App. No.
18/357,045
Granted
Dec 9, 2025
Kind
B2
Abstract

Provided is a solid-state imaging device that includes a first electrode, a second electrode, a photoelectric conversion layer, and a voltage applier. The first electrode includes a plurality of electrodes independent from each other. The second electrode is disposed opposite to the first electrode. The photoelectric conversion layer is disposed between the first electrode and the second electrode. The voltage applier applies different voltages to at least one of the first electrode or the second electrode during a charge accumulation period and a charge non-accumulation period.

Claims (25)

1 . A method of controlling a light detecting device, the method comprising:

turning on a gate of a reset transistor during a charge non-accumulation period; and

turning off the gate of the reset transistor during a charge accumulation period, wherein

the light detecting device comprises a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode,

the light detecting device further comprises an insulating layer between the first electrode and the photoelectric conversion layer,

the first electrode comprises a charge readout electrode and an accumulation electrode, and

the charge readout electrode is electrically coupled with the photoelectric conversion layer via an opening in the insulating layer.

2 . The method of controlling the light detecting device according to claim 1 , further comprising applying different voltages to at least one of the first electrode or the second electrode during the charge accumulation period and the charge non-accumulation period.

3 . The method of controlling the light detecting device according to claim 2 , wherein the charge readout electrode is independent from the accumulation electrode.

4 . The method of controlling the light detecting device according to claim 1 , wherein a voltage across the charge readout electrode and the accumulation electrode is larger during the charge non-accumulation period than during the charge accumulation period.

5 . The method of controlling the light detecting device according to claim 1 , wherein the charge readout electrode serves as a discharge electrode.

6 . The method of controlling the light detecting device according to claim 1 , wherein

the accumulation electrode is divided into a plurality of segments, and

each segment of the plurality of segments is configured to receive a different voltage.

7 . The method of controlling the light detecting device according to claim 1 , wherein

the light detecting device further comprises a semiconductor layer between the photoelectric conversion layer and the insulating layer, and

the charge readout electrode is electrically coupled with the photoelectric conversion layer via the semiconductor layer.

8 . The method of controlling the light detecting device according to claim 1 , wherein

an organic photoelectric transducer is on an inorganic photoelectric transducer,

the organic photoelectric transducer comprises the photoelectric conversion layer, and

the inorganic photoelectric transducer is configured to perform photoelectric conversion in a wavelength band different from a wavelength band of the organic photoelectric transducer.

9 . The method of controlling the light detecting device according to claim 8 , wherein

the inorganic photoelectric transducer is within a semiconductor substrate, and

the organic photoelectric transducer is on a first surface side of the semiconductor substrate.

10 . The method of controlling the light detecting device according to claim 9 , wherein a multilayer wiring layer is on a second surface side of the semiconductor substrate.

Priority Claims (1)
JP 2017-167852 · Aug 31, 2017 · national
Continuity (3)
Continuation 17901994 · Sep 2, 2022
Continuation 16640479
Related Publication 20230370738A1 · Nov 16, 2023
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