IP Library Granted Patent US 12,498,527
Granted Patent B2
US 12,498,527 · App. 18/110,154 · Granted Dec 16, 2025

Packaging microLED optical interconnects

Inventors: Sunghwan Min (Sunnyvale, CA); Robert Kalman (Sunnyvale, CA); Bardia Pezeshki (Sunnyvale, CA); Alexander Tselikov (Sunnyvale, CA)
Assignee: AvicenaTech, Corp.
G02B6/4246G02B6/4228G02B6/4269G02B6/428G02B6/4214G02B6/423
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,498,527
App. No.
18/110,154
Granted
Dec 16, 2025
Kind
B2
Abstract

A packaging and assembly of a parallel optical link is disclosed. The packaging and assembly may have four major parts: assembly of the optical transceiver die, 2.5D package assembly, package attachment to a system printed circuit board, and optical coupling attachment. A frame and a removable lid may be attached to the optical transceiver die. The lid may protect the optical transceiver array of the optical transceiver die, and the frame may help in aligning optical coupling assembly with the optical transceiver array.

Claims (23)

1 . A parallel optical link packaging assembly, comprising:

an optical transceiver die having an integrated circuit wafer with a plurality of through-silicon vias connecting an optoelectronic device array attached on a top surface of the integrated circuit wafer to a bottom surface of the integrated circuit wafer, the integrated circuit wafer including transmitter circuitry and receiver circuitry;

the optoelectronic device array having a plurality of microLEDs and a plurality of photodetectors; and

a frame with a removable lid, the frame attached to the top surface of the integrated circuit wafer, the frame having apertures configured to align one or more optical coupling components with the optoelectronic device array and the removable lid having one or more bridges near the apertures of the frame;

wherein the one or more optical coupling components comprise a multicore optical fiber that is insertable inside one of the apertures of the frame; and

wherein the apertures of the frame have vertical steps configured to align the multicore optical fiber with the optoelectronic device array.

2 . The parallel optical link packaging assembly of claim 1 , wherein the one or more optical coupling components are configured to optically connect the optoelectronic device array with another optical transceiver die.

3 . The parallel optical link packaging assembly of claim 1 , wherein the optical transceiver die along with the frame and the removable lid are encased in a molding compound.

4 . The parallel optical link packaging assembly of claim 1 , wherein the removable lid is partially removable.

5 . The parallel optical link packaging assembly of claim 4 , wherein the removable lid is configured to be removed by mechanical grinding.

6 . The parallel optical link packaging assembly of claim 1 , wherein the optical transceiver die is attached to an interposer having a digital logic die using a 2.5D packaging process.

7 . The parallel optical link packaging assembly of claim 6 , wherein the interposer having the optical transceiver die and the digital logic die is attached to a package substrate using the 2.5D packaging process.

8 . The parallel optical link packaging assembly of claim 7 , wherein the package substrate is attached to a printed circuit board.

9 . The parallel optical link packaging assembly of claim 1 , further comprising a heat sink.

10 . A method of manufacturing a parallel optical link packaging assembly, comprising:

providing an integrated circuit wafer;

fabricating through-silicon vias in the integrated circuit wafer, the through-silicon vias connecting a top surface of the integrated circuit wafer to a bottom surface of said integrated circuit wafer;

attaching an optoelectronic device array on the top surface of the integrated circuit wafer, said optoelectronic device array having a plurality of microLEDs and a plurality of photodetectors;

attaching a frame with a removable lid on the top surface of the integrated circuit wafer, the frame having apertures configured to align one or more optical coupling components with the optoelectronic device array and the removable lid having one or more bridges near the apertures of the frame;

encasing the parallel optical link packaging assembly in a molding compound; and

at least partially removing, by mechanical grinding, the removable lid and a portion of the molding compound on the removable lid.

11 . The method of claim 10 , wherein the one or more optical coupling components comprise a multicore optical fiber that is inserted inside one of the apertures of the frame.

12 . The method of claim 11 , wherein the apertures of the frame have vertical steps that align the multicore optical fiber with the optoelectronic device array.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME FROM AVICENATECH CORP. TO AVICENA TECH, CORP. PREVIOUSLY RECORDED ON REEL 62711 FRAME 43. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 30, 2024
From: MIN, SUNGHWAN; KALMAN, ROBERT; PEZESHKI, BARDIA; TSELIKOV, ALEXANDER
To: AVICENATECH, CORP.
Reel/Frame 067310/0354 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2023
From: MIN, SUNGHWAN; KALMAN, ROBERT; PEZESHKI, BARDIA; TSELIKOV, ALEXANDER
To: AVICENATECH CORP.
Reel/Frame 062711/0043 →
Continuity (2)
Provisional Application 63268061 · Feb 15, 2022
Related Publication 20230258888A1 · Aug 17, 2023
References Cited (14)
US 7192200B2 · Casati · 2007 [cited by examiner]
US 9088128B2 · Kasai · 2015 [cited by examiner]
US 10333623B1 · Liao · 2019 [cited by examiner]
US 12029004B2 · Winzer · 2024 [cited by examiner]
US 20040008952A1 · Kragl · 2004 [cited by examiner]
US 20120138961A1 · Huang et al. · 2012 [cited by applicant]
US 20180100977A1 · Lee · 2018 [cited by applicant]
US 20210091056A1 · Yu et al. · 2021 [cited by applicant]
US 20210104812A1 · Kapusta et al. · 2021 [cited by applicant]
US 20230092821A1 · Karhade · 2023 [cited by examiner]
US 20230204879A1 · Kim · 2023 [cited by examiner]
JP 2007108542A · 2007 [cited by applicant]
International Search Report by International Searching Authority (KIPO) in related PCT Application No. PCT/US2023/013131 dated Jun. 12, 2023. [cited by applicant]
Written Opinion by International Searching Authority (KIPO) in related PCT Application No. PCT/US2023/013131 dated Jun. 12, 2023. [cited by applicant]