IP Library › Granted Patent US 12,506,452
Granted Patent B2
US 12,506,452 · App. 17/908,508 · Granted Dec 23, 2025

Apparatuses and methods involving amplification circuit with push-pull waveshaping operation

Inventors: Juan Rivas-Davila (Palo Alto, CA); Lei Gu (Stanford, CA); Tuofei Chen (Stanford, CA)
Assignee: The Board of Trustees of the Leland Stanford Junior University
H03F3/2176H03F1/56
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Quick Facts
Patent No.
US 12,506,452
App. No.
17/908,508
Granted
Dec 23, 2025
Kind
B2
Abstract

In certain examples, methods and semiconductor structures are directed to circuit-based apparatus in which an amplifier includes stacked, first and second circuit amplification stages to operate out of phase from one another for providing a push-pull operation, with each of the first and second circuit stages including a switching circuit and an impedance path to drive the switching circuit. The apparatus further includes a waveform-shaping circuit to shape, in response to each of the first and second circuit stages, a voltage signal for presentation to the switching circuit. As may be implemented in various more-specific examples, the apparatus may generate a constant output voltage with high efficiency across a wide range of resistive loads.

Claims (37)

1 . An apparatus comprising:

first and second circuit stages configured to operate out of phase from one another and via a push-pull operation;

first and second switching circuits respectively in the first and second circuit stages; and

a waveform-shaping circuit to shape, in response to each of the first and second circuit stages, by tapering transitions of a voltage signal for presentation to the first and second switching circuits.

2 . The apparatus of claim 1 , further including a first inductive impedance path connected to one of two terminals across which the first switching circuit is to switch, and a second inductive impedance path connected to one of two terminals across which the second switching circuit is to switch, wherein the voltage signal is to be presented at the first and second inductive impedance paths to reduce stress experienced by the first and second switching circuits via the tapering of transitions of the voltage signal.

3 . The apparatus of claim 1 , wherein the first and second circuit stages include respective shunt-tuning legs to shunt at least one selected resonant frequency, and wherein the waveform-shaping circuit includes circuitry along a circuit path having end nodes respectively connected to the shunt-tuning legs to provide an effective block of DC current flowing through the circuit path.

4 . The apparatus of claim 1 , wherein the first and second circuit stages are stacked, with each of the first and second circuit stages being coupled to a common DC voltage source and having an effective DC input voltage which is dependent on a DC level provided by the common DC voltage source.

5 . The apparatus of claim 4 , wherein each of the first and second circuit stages has an effective DC input voltage set at one half of the DC level provided by the common DC voltage source.

6 . The apparatus of claim 1 , wherein the first and second circuit stages are stacked relative to one another and the waveform-shaping circuit is connected to the first and second circuit stages and to effect a short circuit therebetween at high frequencies associated with harmonics caused by operation of the first and second circuit stages.

7 . The apparatus of claim 1 , wherein each of the first and second circuit stages includes:

an impedance path having a switch-driving branch to present current to the switching circuit of said each of the first and second circuit stages and having another branch to couple energy to another of the first and second circuit stages via the waveform-shaping circuit; and an output port to couple to a load circuit.

8 . The apparatus of claim 7 , wherein the output port of the first circuit stage is coupled to the first switching circuit via a first LC-based circuit, and an output port of the second circuit stage is coupled to the second switching circuit via a second LC-based circuit which complements the first LC-based circuit, and wherein the first LC-based circuit and the second LC-based circuit are to couple to the load circuit to form a series RLC-based circuit, wherein the load circuit shares in a resistance contribution to the RLC-based circuit that is dominated by the load circuit.

9 . The apparatus of claim 8 , wherein the output ports are to provide a differential signal capable of driving the load circuit.

10 . The apparatus of claim 1 , further including a load circuit, wherein each of the first and second circuit stages includes an output port to couple to the load circuit.

11 . The apparatus of claim 1 , further including an oscillating- or frequency-signal driver circuitry to drive each of the switching circuits at its gate or control node, so that each of the switching circuits is out of phase relative to a phase of another of said each of the switching circuits.

12 . The apparatus of claim 11 , wherein the respective switching circuits of the first and second circuit stages are to operate out of phase from one another by approximately 180 degrees.

13 . The apparatus of claim 1 , wherein each of the respective first and second circuit stages further includes a single-ended inverter circuit, including a field-effect transistor, as part of an impedance path configured to present current to the respective one of the first and second switching circuits.

14 . The apparatus of claim 1 , wherein the waveform-shaping circuit has a frequency-dependent inductor-capacitor impedance configuration and includes a first terminal coupled to the first switching circuit and includes a second opposing terminal coupled to the second switching circuit.

15 . The apparatus of claim 1 , wherein the first and second switching circuits are respectively coupled to first and second impedance paths, the first and second impedance paths being respectively associated with first and second inductance values, and wherein the first inductive value is at least twice as great as the second inductance value, and wherein the first and second circuit stages form an amplifier to manifest certain performance as a function of the first and second inductance values.

16 . The apparatus of claim 15 , wherein said first and second inductance values are set for the amplifier to, minimize or optimize at least one of or a combination from among the following: circulating energy, power consumption or power loss, and input EMI and potential oscillations.

17 . The apparatus of claim 1 , wherein the first and second switching circuits are respectively coupled to first and second impedance paths, the first and second impedance paths being respectively associated with first and second inductance values, and wherein the first inductive value is greater than the second inductance value by a factor in a range from three times (3×) to five times (5×) the second inductance value.

18 . The apparatus of claim 1 , wherein at least one of the first and second switching circuits includes a GaN-based (Gallium Nitride) field-effect transistor.

19 . The apparatus of claim 1 , wherein neither of the first and second switching circuits includes a GaN-based (Gallium Nitride) field-effect transistor.

20 . The apparatus of claim 1 , wherein the waveform-shaping circuit is part of an amplifier and the amplifier is to provide a power efficiency of at least 88%.

21 . The apparatus of claim 1 , wherein the waveform-shaping circuit is part of an amplifier and the amplifier is to provide a power efficiency of at least 80%; and less than 95%.

22 . The apparatus of claim 1 , wherein the first and second circuit stages and the waveform-shaping circuit are to drive a load wirelessly at a frequency greater than or equal to 1 Megahertz.

23 . The apparatus of claim 1 , wherein the first and second circuit stages and the waveform-shaping circuit are to drive a load wirelessly at a frequency corresponding to approximately 6.78 Megahertz or a multiple of approximately 6.78 Megahertz.

24 . The apparatus of claim 1 , wherein at least one of the first and second switching circuits includes a field effect transistor (FET), and a source/drain node of the FET is to be set at a constant voltage level.

25 . The apparatus of claim 1 , wherein the first and second circuit stages and the waveform-shaping circuit are to drive a load wirelessly, and the load includes or corresponds to an appliance which is one of: a biomedical implant circuit; a medical MRI (magnetic resonance imaging circuit); a circuit to operate a vehicle (e.g., automobile, aircraft, train); and a DC-operated machine to assemble components (e.g., robot, portable sensor/camera).

26 . An apparatus comprising:

a first circuit stage and a second circuit stage, the first circuit stage to operate out of phase from the second circuit stage and via a push-pull operation;

each of the first and second circuit stages having a respective front-end power or voltage section which is stacked in series relative to the other of the first and second circuit stages; and

a waveform-shaping circuit to shape, in response to each of the first and second circuit stages, by tapering transitions of a voltage signal for presentation to first and second switching circuits.

27 . The apparatus of claim 1 , wherein the respective phases of the first circuit stage and the second circuit stage interleave, and wherein each of the respective front-end power or voltage sections sets or provides a DC voltage operating level, wherein the DC voltage operating levels are approximately equal.

28 . A method comprising:

operating first and second signal-amplification circuit stages out of phase from one another and via a push-pull operation, wherein the first and second signal-amplification circuit stages including respective first and second switching circuits; and

a waveform-shaping circuit shaping, in response to each of the first and second circuit stages, by tapering transitions of a voltage signal for presentation to the first and second switching circuits.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2022
From: RIVAS-DAVILA, JUAN; GU, LEI; CHEN, TUOFEI
To: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY
Reel/Frame 060970/0771 →
Continuity (2)
Provisional Application 62988745 · Mar 12, 2020
Related Publication 20230122538A1 · Apr 20, 2023
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