Method and structures to reduce resistivity in three-dimensional structures for microelectronic workpieces using material deposited in recesses at edges of holes in a multilayer stack
In certain embodiments, a 3D structure for a microelectronic workpiece includes a multilayer stack that includes polysilicon layers separated by other layers, holes formed within the multilayer stack, recesses formed within the polysilicon layers at edges of the holes, conductive material deposited within the recesses to form outer layers within the holes, and plugs formed adjacent the outer layers within the holes.
1 . A method for forming three-dimensional (3D) structures for a microelectronic workpiece, comprising:
forming holes within a multilayer stack, the multilayer stack comprising polysilicon layers separated by other layers;
forming recesses within the polysilicon layers at edges of the holes;
depositing a conductive material within the recesses to form outer layers within the holes, wherein the conductive material deposited within the recesses is deposited in direct contact with the polysilicon layers within the recesses and is conductive as initially deposited in direct contact with the polysilicon layers within the recesses, the conductive material deposited within the recesses being an electrically conductive material; and
forming plugs adjacent to the outer layers within the holes.
2 . The method of claim 1 , wherein the multilayer stack comprises alternating oxide layers and polysilicon layers.
3 . The method of claim 1 , wherein the conductive material deposited within the recesses comprises titanium nitride.
4 . The method of claim 1 , wherein the conductive material deposited within the recesses comprises at least one of titanium silicon nitride (TiSiN), tantalum nitride (TaN), aluminum-doped titanium carbide (TiAlC), titanium oxynitride (TiON), titanium carbon nitride (TiCN), or titanium aluminum nitride (TiAlN).
5 . The method of claim 1 , wherein:
the holes comprise channel holes for three-dimensional memory cells; and
the polysilicon layers and the conductive material within the recesses are used to provide gates for the three-dimensional memory cells.
6 . The method of claim 5 , wherein the three-dimensional memory cells comprise vertical NAND memory cells.
7 . The method of claim 1 , wherein the plugs comprise one or more of the following film layers: aluminum oxide layers, silicon nitride layers, oxide layers, or silicon layers.
8 . The method of claim 1 , wherein forming the recesses comprises performing one or more wet etch processes, plasma etch processes, reactive ion etch processes, or combinations of etch processes.
9 . The method of claim 1 , wherein depositing the conductive material within the recesses comprises performing one or more atomic layer deposition processes, chemical vapor deposition processes, plasma deposition processes, or combinations of deposition processes.
10 . The method of claim 1 , wherein a target level of resistivity is achieved across the structures by depositing the conductive material within the recesses formed in the polysilicon layers.
11 . A method of forming three-dimensional (3D) structures for a microelectronic workpiece, comprising:
forming, over a substrate, a multilayer stack that comprises polysilicon layers and insulating layers in an alternating stacked arrangement;
forming channel holes for 3D memory cells, the channel holes being formed within the multilayer stack and extending into the substrate;
forming outer layers within the channel holes, the outer layers comprising fill material deposited within recesses that are formed within the polysilicon layers at edges of the channel holes and within substrate recesses that are formed within the substrate in the channel holes, the fill material having a lower resistivity than the polysilicon layers, the polysilicon layers and the fill material within the recesses configured to provide gates for the 3D memory cells, wherein the fill material deposited within the recesses directly contacts the polysilicon layers within the recesses and has the lower resistivity as initially deposited; and
forming plugs adjacent the outer layers within the channel holes, the plugs comprising multiple material layers, the multiple material layers for the plugs comprising silicon layers configured to provide channels for the 3D memory cells, at least a portion of the fill material in the substrate recesses remaining between the plugs and the substrate and contacting the plugs after forming the plugs adjacent the outer layers within the channel holes.
12 . The method of claim 11 , wherein the insulating layers are oxide layers such that the multilayer stack is an oxide-polysilicon-oxide-polysilicon (OPOP) stack.
13 . The method of claim 11 , wherein the fill material deposited within the recesses comprises titanium nitride.
14 . The method of claim 11 , wherein the fill material deposited within the recesses comprises at least one of titanium silicon nitride (TiSiN), tantalum nitride (TaN), aluminum-doped titanium carbide (TiAlC), titanium oxynitride (TiON), titanium carbon nitride (TiCN), or titanium aluminum nitride (TiAlN).
15 . The method of claim 11 , wherein the multiple material layers for the plugs comprise a dielectric layer comprising a low-k dielectric material.
16 . The method of claim 11 , wherein the 3D memory cells comprise vertical NAND memory cells.
17 . The method of claim 11 , wherein the recesses are formed at least in part by performing one or more wet etch processes, plasma etch processes, reactive ion etch processes, or combinations of etch processes.
18 . The method of claim 11 , wherein the fill material is deposited within the recesses at least in part by performing one or more atomic layer deposition processes, chemical vapor deposition processes, plasma deposition processes, or combinations of deposition processes.
19 . The method of claim 11 , wherein a target level of resistivity is achieved across the structures by depositing the fill material within the recesses formed in the polysilicon layers.
20 . A method of forming three-dimensional (3D) structures for a microelectronic workpiece, comprising:
forming a multilayer stack that comprises alternating oxide layers and polysilicon layers;
forming holes within the multilayer stack;
forming recesses within the polysilicon layers at edges of the holes;
depositing conductive material within the recesses to form outer layers within the holes, wherein the conductive material deposited within the recesses is deposited in direct contact with the polysilicon layers within the recesses and is conductive as initially deposited in direct contact with the polysilicon layers within the recesses, the conductive material deposited within the recesses comprising metal and being an electrically conductive material; and
forming plugs adjacent to the outer layers within the holes; and
providing a 3D memory structure in which remaining portions of the polysilicon layers and the conductive material within the recesses and deposited directly on the polysilicon layers within the recesses provide gates, and in which at least a portion of the plugs provide act as channels.