High-performance, high-capacity memory modules and systems
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
1 . A memory module comprising:
module data connections;
module control connections;
an address-buffer die coupled to the module control connections via a module control interface;
a first memory die coupled to the address-buffer die via a first memory-die control interface;
a second memory die coupled to the address-buffer die via a second memory-die control interface; and
a data-buffer die coupled between the module data connections and both the first memory die and the second memory die, the data-buffer die supporting:
a first-width-data mode to steer first-width data on the module data connections to both the first memory die and the second memory die; and
a second-width-data mode to steer second-width data on the module data connections to only one of the first memory die and the second memory die;
the address-buffer die simultaneously asserting a first chip-select signal on the first memory-die control interface and a second chip-select signal the second memory-die control interface in the first-width-data mode and asserting only one of the first chip-select signal and the second chip-select signal in the second-width-data mode.
2 . The memory module of claim 1 , the data-buffer die including a data-buffer register to store a mode value selecting one of the first-width-data mode and the second-width-data mode.
3 . The memory module of claim 2 , wherein the address-buffer die loads the data-buffer register responsive to control signals from the module control connections.
4 . The memory module of claim 1 , wherein the address-buffer die selects the one of the first memory-die control interface and the second memory-die control interface in the second-width-data mode responsive to a control signal on the module control connections.
5 . The memory module of claim 1 , wherein the data-buffer die is coupled to a number of the module data connections and is coupled to each of the first memory die and the second memory die by a half the number of the module data connections.
6 . The memory module of claim 5 , wherein the number is eight.
7 . The memory module of claim 1 , the address-buffer die including an address-buffer register to store a mode value selecting one of the first-width-data mode and the second-width-data mode.
8 . A memory comprising:
data connections;
control connections;
an address-buffer die coupled to the control connections;
a first memory die coupled to the address-buffer die;
a second memory die coupled to the address-buffer die; and
a data-buffer die coupled between the data connections and both the first memory die and the second memory die, the data-buffer die supporting:
a first-width-data mode to steer first-width data on the data connections simultaneously to both the first memory die and the second memory die; and
a second-width-data mode to steer second-width data on the data connections to only one of the first memory die and the second memory die at a time;
the address-buffer die simultaneously asserting a first chip-select signal on the first memory die and a second chip-select signal the second memory die in the first-width-data mode and asserting only one of the first chip-select signal and the second chip-select signal in the second-width-data mode.
9 . The memory of claim 8 , the data-buffer die including a data-buffer register to store a mode value selecting one of the first-width-data mode and the second-width-data mode.
10 . The memory of claim 9 , wherein the address-buffer die loads the data-buffer register responsive to control signals from the control connections.
11 . The memory of claim 8 , wherein the address-buffer die selects the one of the first memory die and the second memory die in the second-width-data mode responsive to a control signal on the control connections.
12 . The memory of claim 8 , wherein the data-buffer die is coupled to a number of the data connections and is coupled to each of the first memory die and the second memory die by a half the number of the data connections.
13 . The memory of claim 12 , wherein the number is eight.
14 . The memory of claim 8 , the address-buffer die including an address-buffer register to store a mode value selecting one of the first-width-data mode and the second-width-data mode.
15 . A memory module comprising:
a printed-circuit (PC) board having a first board side, a second board side, module data connections, and module control connections;
an address-buffer die coupled to the module control connections;
a first memory die coupled to the address-buffer die;
a second memory die coupled to the address-buffer die; and
a data-buffer die coupled between the module data connections and both the first memory die and the second memory die, the data-buffer die supporting:
a first-width-data mode to steer first-width data on the module data connections to both the first memory die and the second memory die; and
a second-width-data mode to steer second-width data on the module data connections to only one of the first memory die and the second memory die;
the address-buffer die simultaneously asserting a first chip-select signal to the first memory die and a second chip-select signal to the second memory die in the first-width-data mode and asserting only one of the first chip-select signal and the second chip-select signal in the second-width-data mode.
16 . The memory module of claim 15 , the data-buffer die including a data-buffer register to store a mode value selecting one of the first-width-data mode and the second-width-data mode.
17 . The memory module of claim 16 , wherein the address-buffer die loads the data-buffer register responsive to control signals from the module control connections.
18 . The memory module of claim 15 , wherein the address-buffer die selects the one of the first memory die and the second memory die in the second-width-data mode responsive to a control signal on the module control connections.
19 . The memory module of claim 15 , wherein the data-buffer die is coupled to a number of the module data connections and is coupled to each of the first memory die and the second memory die by a half the number of the module data connections.
20 . The memory module of claim 19 , wherein the number is eight.