Field-effect transistors with a high-temperature hardmask and self-aligned p-shield
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer in the trench, and a dielectric layer on the top surface of the semiconductor substrate. The dielectric layer includes an opening that is aligned with the trench in the semiconductor substrate, and the dielectric layer comprises a material with a melting point that is greater than or equal to 2000° C.
1 . A structure for a field-effect transistor, the structure comprising:
a semiconductor substrate including a top surface, a first doped region adjacent to the top surface, and a first trench that extends through the first doped region, the semiconductor substrate comprising a wide bandgap semiconductor material;
a first gate structure comprising a gate conductor layer in the first trench; and
a first dielectric layer on the top surface of the semiconductor substrate, the first dielectric layer including an opening that is aligned with the first trench in the semiconductor substrate, and the first dielectric layer comprising a material with a melting point that is greater than or equal to 2000° C.,
wherein the first trench includes a trench bottom, a first sidewall, and a second sidewall that adjoins the first sidewall, the semiconductor substrate further includes a second doped region adjacent to the trench bottom of the first trench and a third doped region adjacent to the first sidewall of the first trench, and the third doped region extends from the second doped region to the top surface.
2 . The structure of claim 1 wherein the first gate structure further includes a silicide layer on the gate conductor layer.
3 . The structure of claim 2 wherein the silicide layer is disposed at least in part inside the opening in the first dielectric layer, the opening in the first dielectric layer has a first width dimension, and the silicide layer has a second width dimension that is substantially equal to the first width dimension.
4 . The structure of claim 2 wherein the gate conductor layer includes a recess, and the silicide layer is disposed in the recess.
5 . The structure of claim 4 further comprising:
a second dielectric layer disposed inside the opening on the silicide layer.
6 . The structure of claim 1 wherein the semiconductor substrate further includes a second trench having sidewall adjacent to the second sidewall of the first trench and a channel region between the second sidewall of the first trench and the sidewall of the second trench.
7 . The structure of claim 1 wherein the first doped region, the second doped region, and the third doped region have the same conductivity type.
8 . The structure of claim 1 wherein the semiconductor substrate further includes a second trench, a third trench, a first channel region between the first trench and the second trench, and a second channel region between the first trench and the third trench, and further comprising:
a second gate structure including a gate conductor layer in the second trench; and
a third gate structure including a gate conductor layer in the third trench.
9 . The structure of claim 1 wherein the material is an electrical insulator.
10 . The structure of claim 1 wherein the material comprises aluminum nitride.
11 . The structure of claim 1 wherein the material comprises polycrystalline silicon carbide.
12 . The structure of claim 1 wherein the first dielectric layer includes a first sublayer and a second sublayer that is disposed on the first sublayer, the first sublayer comprises aluminum oxide, and the second sublayer comprises aluminum nitride or polycrystalline silicon carbide.
13 . The structure of claim 1 wherein the first dielectric layer includes a first sublayer and a second sublayer that is disposed on the first sublayer, the first sublayer comprises aluminum nitride, and the second sublayer comprises polycrystalline silicon carbide.
14 . The structure of claim 1 wherein the wide bandgap semiconductor material comprises silicon carbide.
15 . A structure for a field-effect transistor, the structure comprising:
a semiconductor substrate including a top surface, a first doped region adjacent to the top surface, and a trench that extends through the first doped region, the semiconductor substrate comprising a wide bandgap semiconductor material;
a gate structure comprising a gate conductor layer in the trench;
a first dielectric layer on the top surface of the semiconductor substrate, the first dielectric layer including an opening that is aligned with the trench in the semiconductor substrate, and the first dielectric layer comprising a material with a melting point that is greater than or equal to 2000° C.; and
a second dielectric layer on the gate conductor layer, the second dielectric layer disposed at least in part inside the opening in the first dielectric layer.
16 . The structure of claim 15 wherein the opening in the first dielectric layer has a first width dimension, and the second dielectric layer has a second width dimension that is substantially equal to the first width dimension.
17 . The structure of claim 15 wherein the gate conductor layer includes a recess, and the second dielectric layer is disposed in the recess.
18 . The structure of claim 15 wherein the second dielectric layer extends above the top surface of the semiconductor substrate.
19 . The structure of claim 15 wherein the trench includes a trench bottom, a first sidewall, and a second sidewall that adjoins the first sidewall, the semiconductor substrate further includes a second doped region adjacent to the trench bottom of the trench and a third doped region adjacent to the first sidewall of the trench, and the third doped region extends from the second doped region to the top surface.
20 . A method of forming a structure for a field-effect transistor, the method comprising:
forming a doped region adjacent to a top surface of a semiconductor substrate, wherein the semiconductor substrate comprises a wide bandgap semiconductor material;
forming a dielectric layer on the top surface of the semiconductor substrate, wherein the dielectric layer comprises a material with a melting point that is greater than or equal to 2000° C.;
forming an opening in the dielectric layer;
forming a trench in the semiconductor substrate that extends through the doped region, wherein the opening in the dielectric layer is aligned with the trench in the semiconductor substrate; and
forming a gate structure comprising a gate conductor layer in the trench, wherein the dielectric layer is present on the top surface of the semiconductor substrate during formation of the gate structure.