Semiconductor devices and methods of manufacturing thereof
A method for fabricating a semiconductor device includes exposing one or more surfaces of a conduction channel of a transistor; overlaying the one or more surfaces with a dielectric interfacial layer; overlaying the dielectric interfacial layer with a blocking layer; performing a first annealing process to densify the dielectric interfacial layer; overlaying the blocking layer with a first high-k dielectric layer; forming one or more threshold voltage modulation layers over the first high-k dielectric layer; performing a second annealing process to adjust a doping profile of the first high-k dielectric layer; and overlaying the first high-k dielectric layer with a second high-k dielectric layer.
1 . A method for fabricating a semiconductor device, comprising:
exposing one or more surfaces of a conduction channel of a transistor;
overlaying the one or more surfaces with a dielectric interfacial layer;
overlaying the dielectric interfacial layer with a blocking layer;
performing a first annealing process to densify the dielectric interfacial layer;
overlaying the blocking layer with a first high-k dielectric layer;
forming one or more threshold voltage modulation layers over the first high-k dielectric layer;
performing a second annealing process to adjust a doping profile of the first high-k dielectric layer; and
overlaying the first high-k dielectric layer with a second high-k dielectric layer.
2 . The method of claim 1 , wherein the blocking layer includes a high-k dielectric material selected from a group consisting of: aluminum oxide (Al 2 O 3 ), scandium oxide (ScO 2 ), yttrium oxide (Y 2 O 3 ), lutetium(III) oxide (Lu 2 O 3 ), thulium(III) oxide (Tm 2 O 3 ), gadolinium(III) oxide (Gd 2 O 3 ), erbium(III) oxide (Er 2 O 3 ), magnesium oxide (MgO), calcium oxide (CaO), zirconium silicate (ZrSiO 4 ).
3 . The method of claim 1 , wherein the blocking layer is configured to prevent oxygen from reaching the dielectric interfacial layer, thereby maintaining an originally formed thickness of the dielectric interfacial layer.
4 . The method of claim 1 , wherein the dielectric interfacial layer has a first dielectric constant and the blocking layer has a second dielectric constant, the second dielectric constant being greater than the first dielectric constant.
5 . The method of claim 1 , further comprising performing a wet etching process to form the dielectric interfacial layer, wherein the wet etching process includes applying a heated chemical mixture on the one or more surfaces of the conduction channel, and wherein the chemical mixture includes at least one of: ammonium hydroxide (NH 4 OH), hydrogen chloride (HCl), sulfuric acid (H 2 SO 4 ), or hydrogen peroxide (H 2 O 2 ).
6 . The method of claim 5 , wherein an originally formed thickness of the dielectric interfacial layer is equal to or less than 5 angstroms (Å).
7 . The method of claim 1 , wherein the conduction channel includes a plurality of nanostructures vertically spaced from one another.
8 . The method of claim 1 , following the step of performing the second annealing process, further comprising removing the one or more threshold voltage modulation layers.
9 . The method of claim 1 , wherein the one or more threshold voltage modulation layers are selected from a group consisting of: lanthanum (III) oxide (La 2 O 3 ), lutetium oxide (LuO), scandium oxide (ScO), yttrium oxide (Y 2 O 3 ), Thulium (III) oxide (Tm 2 O 3 ), gadolinium(III) oxide (Gd 2 O 3 ), and combinations thereof.
10 . The method of claim 1 , wherein the one or more threshold voltage modulation layers are selected from a group consisting of: zinc oxide (ZnO), germanium oxide (GeO), aluminum(II) oxide (AlO), titanium(II) oxide (TiO), vanadium(II) oxide (VO), and combinations thereof.
11 . The method of claim 1 , following the step of overlaying the first high-k dielectric layer with the second high-k dielectric layer, further comprising:
forming one or more work function metal layers over the second high-k dielectric layer; and
forming an interconnect structure in contact with at least a portion of the one or more work function metal layers.
12 . A method for fabricating a gate all around transistor, comprising:
forming a plurality of conduction channels between a source region and a drain region;
overlaying the conduction channels with a dielectric interfacial layer;
overlaying the dielectric interfacial layer with a barrier dielectric configured to prevent oxygen from reaching the dielectric interfacial layer;
densifying the dielectric interfacial layer at a first annealing temperature below a recrystallization temperature of the barrier dielectric;
overlaying the barrier dielectric with a high-k dielectric layer;
forming a threshold voltage modulation layer over the high-k dielectric layer;
performing an annealing process to adjust a doping profile of the high-k dielectric layer; and
removing the threshold voltage modulation layer subsequent to the annealing process.
13 . The method of claim 12 , further comprising:
overlaying the high-k dielectric layer with a second high-k dielectric layer, subsequent to the removal of the threshold voltage modulation layer.
14 . The method of claim 12 , wherein the barrier dielectric layer includes a high-k dielectric material selected from a group consisting of: aluminum oxide (Al 2 O 3 ), scandium oxide (ScO 2 ), yttrium oxide (Y 2 O 3 ), lutetium(III) oxide (Lu 2 O 3 ), thulium(III) oxide (Tm 2 O 3 ), gadolinium(III) oxide (Gd 2 O 3 ), erbium(III) oxide (Er 2 O 3 ), magnesium oxide (MgO), calcium oxide (CaO), zirconium silicate (ZrSiO 4 ).
15 . The method of claim 12 , wherein the barrier dielectric layer is configured to maintain an originally formed thickness of the dielectric interfacial layer that is equal to or less than 5 angstroms (Å).
16 . The method of claim 12 , wherein the dielectric interfacial layer has a first dielectric constant and the barrier dielectric layer has a second dielectric constant, the second dielectric constant being greater than the first dielectric constant.
17 . The method of claim 12 , wherein the plurality of conduction channels comprise nanostructures vertically spaced from one another by a portion of a gate structure.
18 . The method of claim 12 , wherein:
the threshold voltage modulation layer comprises materials selected from a group consisting of: lanthanum(III) oxide (La 2 O 3 ), lutetium oxide (LuO), scandium oxide (ScO), yttrium oxide (Y 2 O 3 ), Thulium(III) oxide (Tm 2 O 3 ), gadolinium(III) oxide (Gd 2 O 3 ), zinc oxide (ZnO), germanium oxide (GeO), aluminum(II) oxide (AlO), titanium(II) oxide (TiO), vanadium(II) oxide (VO), and combinations thereof.
19 . A method for fabricating a transistor, comprising:
exposing a surface of a conduction channel;
overlaying the surface with a dielectric interfacial layer;
overlaying the dielectric interfacial layer with a blocking layer;
performing a first annealing process to densify the dielectric interfacial layer;
overlaying the blocking layer with a gate dielectric layer;
using a threshold voltage modulation layer to adjust a doping profile of the gate dielectric layer; and
forming a work function metal layer over the gate dielectric layer.
20 . The method of claim 19 , wherein the gate dielectric layer comprises a plurality of sublayers, including at least one sublayer in contact with the work function metal layer, and further comprising:
forming an interconnect structure in contact with the work function metal layer.