IP Library › Granted Patent US 12,315,730
Granted Patent B2
US 12,315,730 · App. 17/741,270 · Granted May 27, 2025

Semiconductor devices with metal intercalated high-k capping

Inventors: Chandrashekhar Prakash Savant (Hsinchu, TW); Kin Shun Chong (Hsinchu, TW); Tien-Wei Yu (Hsinchu, TW); Chia-Ming Tsai (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/28088H10D64/667
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Quick Facts
Patent No.
US 12,315,730
App. No.
17/741,270
Granted
May 27, 2025
Kind
B2
Abstract

A method includes providing a structure having a substrate, a semiconductor channel layer over the substrate, an interfacial oxide layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial oxide layer, wherein the semiconductor channel layer includes germanium. The method further includes forming a metal nitride layer over the high-k gate dielectric layer and performing a first treatment to the structure using a metal-containing gas. After the performing of the first treatment, the method further includes depositing a silicon layer over the metal nitride layer; and then annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer. The metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas.

Claims (53)

1. A method comprising:

providing a structure having a substrate, a semiconductor channel layer over the substrate, an interfacial oxide layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial oxide layer, wherein the semiconductor channel layer includes germanium;

forming a metal nitride layer over the high-k gate dielectric layer;

performing a first treatment to the structure using a metal-containing gas;

after the performing of the first treatment, depositing a silicon layer over the metal nitride layer; and

after the depositing of the silicon layer, annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer, wherein the metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas.

2. The method of claim 1 , wherein the semiconductor channel layer includes silicon germanium or germanium tin.

3. The method of claim 2 , wherein the semiconductor channel layer includes silicon germanium and the metal-containing gas includes MoCl 4 O, WF 6 , TiCl 4 , or PDMAT.

4. The method of claim 2 , wherein the semiconductor channel layer includes germanium tin and the metal-containing gas includes MoCl 4 O or WF 6 .

5. The method of claim 1 , wherein the metal nitride layer includes titanium nitride, tantalum nitride, or titanium silicon nitride.

6. The method of claim 1 , wherein the metal nitride layer is formed after the performing of the first treatment and before the depositing of the silicon layer.

7. The method of claim 6 , after the metal nitride layer is formed and before the depositing of the silicon layer, further comprising:

performing a second treatment to the structure using the metal-containing gas.

8. The method of claim 7 , before the depositing of the silicon layer, further comprising:

forming a second metal nitride layer after the performing of the second treatment; and

performing a third treatment to the structure using the metal-containing gas after the second metal nitride layer is formed.

9. The method of claim 1 , further comprising:

performing a second treatment to the structure using a silicon-containing gas immediately after the performing of the first treatment.

10. The method of claim 9 , before the depositing of the silicon layer and after the performing of the second treatment, further comprising:

depositing a second silicon layer over the metal nitride layer.

11. The method of claim 10 , before the depositing of the silicon layer and after the depositing of the second silicon layer, further comprising:

performing a third treatment to the structure using the metal-containing gas and the silicon-containing gas.

12. The method of claim 1 , further comprising:

depositing a second silicon layer over the metal nitride layer before the performing of the first treatment.

13. The method of claim 12 , after the performing of the first treatment and before the depositing of the silicon layer, further comprising:

depositing a third silicon layer over the second silicon layer; and

performing a second treatment to the structure using the metal-containing gas.

14. The method of claim 1 , further comprising:

removing the silicon layer and the metal nitride layer and keeping at least a portion of the metal intermixing layer in the structure; and

forming a metal gate electrode over the high-k gate dielectric layer and the metal intermixing layer.

15. A method comprising:

providing a structure having a substrate, a semiconductor channel layer over the substrate, an interfacial oxide layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial oxide layer, wherein the semiconductor channel layer includes germanium;

forming a metal nitride layer over the high-k gate dielectric layer;

after the forming of the metal nitride layer, performing a first treatment to the structure using a metal-containing gas;

after the performing of the first treatment, depositing a passivation layer over the metal nitride layer, wherein the passivation layer includes silicon;

after the depositing of the passivation layer, annealing the structure such that a metal intermixing layer is formed over the high-k gate dielectric layer, wherein the metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species from the metal-containing gas;

removing the passivation layer and the metal nitride layer and keeping at least a portion of the metal intermixing layer in the structure; and

forming a metal gate electrode over the high-k gate dielectric layer and the metal intermixing layer.

16. The method of claim 15 , wherein the metal nitride layer includes titanium nitride, tantalum nitride, or titanium silicon nitride, and the metal-containing gas includes MoCl 4 O, WF 6 , TiCl 4 , or PDMAT.

17. The method of claim 15 , before the depositing of the passivation layer, further comprising:

depositing a silicon layer over the metal nitride layer.

18. A method, including:

providing a structure having a semiconductor channel layer, an interfacial layer over the semiconductor channel layer, and a high-k gate dielectric layer over the interfacial layer, wherein the semiconductor channel layer includes germanium;

forming a metal nitride layer over the high-k gate dielectric layer;

depositing a first silicon layer over the metal nitride layer;

performing a treatment to the structure using a metal-containing gas;

forming a second silicon layer over the metal nitride layer;

performing an annealing process to form a metal intermixing layer over the high-k gate dielectric layer;

removing layers down to the metal intermixing layer; and

forming a metal gate electrode over the high-k gate dielectric layer and the metal intermixing layer.

19. The method of claim 18 , wherein the metal intermixing layer includes a metal oxide having metal species from the high-k gate dielectric layer and additional metal species.

20. The method of claim 19 , wherein the treatment is a first treatment, and

wherein the method further comprises performing a second treatment to the structure using the metal-containing gas before forming the second silicon layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2022
From: SAVANT, CHANDRASHEKHAR PRAKASH; CHONG, KIN SHUN; YU, TIEN-WEI; TSAI, CHIA-MING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060832/0001 →
Continuity (2)
Provisional Application 63283092 · Nov 24, 2021
Related Publication 20230162983A1 · May 25, 2023
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