Apparatus, system, and method for reducing the footprints of circuits that protect against the antenna effect and electrostatic discharge
An exemplary apparatus includes a through-silicon via (TSV) and circuit that protects against the antenna effect and electrostatic discharge (ESD). The circuit can include a plurality of transistors whose gates are each electrically coupled to a signal that passes through the TSV. Various other apparatuses, systems, and methods are also disclosed.
1 . An apparatus comprising:
a through-silicon via (TSV); and
a circuit that protects against an antenna effect and electrostatic discharge (ESD), the circuit comprising a plurality of transistors whose gates are each electrically coupled to a signal that passes through the TSV.
2 . The apparatus of claim 1 , further comprising:
a plurality of additional TSVs; and
a plurality of additional circuits that protect against the antenna effect and the ESD, each of the plurality of additional circuits comprising a plurality of additional transistors whose gates are each electrically coupled to an additional signal that passes through at least one of the plurality of additional TSVs.
3 . The apparatus of claim 1 , wherein the plurality of transistors comprises:
a first transistor whose terminals are collectively coupled to the signal and a positive supply voltage;
a second transistor whose terminals are collectively coupled to the signal and a negative supply voltage or an electrical ground; and
a third transistor whose terminals are collectively coupled to the signal and the negative supply voltage or the electrical ground.
4 . The apparatus of claim 1 , wherein the plurality of transistors comprises a set of three field-effect transistors (FETs) whose gates are each directly electrically coupled to the signal.
5 . The apparatus of claim 4 , wherein the set of three FETs comprises:
a p-channel metal-oxide-semiconductor FET (MOSFET) whose gate, source, and drain are each electrically coupled to the signal and whose bulk is electrically coupled to a positive supply voltage;
a first n-channel MOSFET whose gate, source, and drain are each electrically coupled to the signal and whose bulk is electrically coupled to a negative supply voltage or an electrical ground; and
a second n-channel MOSFET whose gate, source, and drain are each electrically coupled to the signal and whose bulk is electrically coupled to the negative supply voltage or the electrical ground.
6 . The apparatus of claim 1 , further comprising a very large scale integration (VLSI) device that includes the TSV and the circuit.
7 . The apparatus of claim 6 , wherein:
the VLSI device comprises a plurality of standard cells that share one or more dimensions in common with one another; and
the circuit fits inside a standard cell included in the plurality of standard cells.
8 . The apparatus of claim 1 , further comprising an additional circuit electrically coupled to the signal.
9 . The apparatus of claim 8 , wherein the additional circuit comprises a tri-state buffer electrically coupled to the signal.
10 . The apparatus of claim 8 , wherein the additional circuit comprises at least a portion of a memory device.
11 . A system comprising:
a through-silicon via (TSV); and
a plurality of dies electrically coupled to one another by the TSV, the plurality of dies comprising a die that implements a circuit that:
protects against an antenna effect and electrostatic discharge (ESD); and
includes a plurality of transistors whose gates are each electrically coupled to a signal that passes through the TSV.
12 . The system of claim 11 , further comprising a plurality of additional TSVs, wherein the die further implements a plurality of additional circuits that protect against the antenna effect and the ESD, each of the plurality of additional circuits comprising a plurality of additional transistors whose gates are each electrically coupled to an additional signal that passes through at least one of the plurality of additional TSVs.
13 . The system of claim 11 , wherein the plurality of transistors comprises:
a first transistor whose terminals are collectively coupled to the signal and a positive supply voltage;
a second transistor whose terminals are collectively coupled to the signal and a negative supply voltage or an electrical ground; and
a third transistor whose terminals are collectively coupled to the signal and the negative supply voltage or the electrical ground.
14 . The system of claim 11 , wherein the plurality of transistors comprises a set of three field-effect transistors (FETs) whose gates are each electrically coupled to the signal.
15 . The system of claim 14 , wherein the set of three FETs comprises:
a p-channel metal-oxide-semiconductor FET (MOSFET) whose gate, source, and drain are each electrically coupled to the signal and whose bulk is electrically coupled to a positive supply voltage;
a first n-channel MOSFET whose gate, source, and drain are each electrically coupled to the signal and whose bulk is electrically coupled to a negative supply voltage or an electrical ground; and
a second n-channel MOSFET whose gate, source, and drain are each electrically coupled to the signal and whose bulk is electrically coupled to the negative supply voltage or the electrical ground.
16 . The system of claim 11 , further comprising a very large scale integration (VLSI) device that includes the TSV and the plurality of dies.
17 . The system of claim 16 , wherein:
the VLSI device comprises a plurality of standard cells that share one or more dimensions in common with one another; and
the circuit fits inside a standard cell included in the plurality of standard cells.
18 . The system of claim 11 , further comprising an additional circuit electrically coupled to the signal.
19 . The system of claim 18 , wherein the additional circuit comprises a tri-state buffer electrically coupled to the signal.
20 . A method comprising:
forming a through-silicon via (TSV) on a die;
creating, on the die, a circuit that protects against an antenna effect and electrostatic discharge (ESD) through a plurality of transistors; and
electrically coupling gates of the plurality of transistors to a signal that passes through the TSV.