Semiconductor structure
A semiconductor structure includes a substrate, a gate structure, source/drain epitaxial structures, a contact structure, a first via structure, a metal line, a hard mask layer, a spacer layer, and a second via structure. The gate structure is formed over the substrate. The source/drain epitaxial structures are formed on opposite sides of the gate structure. The contact structure is formed over one of the source/drain epitaxial structures. The first via structure is formed over the contact structure. The metal line is electrically connected to the first via structure. The hard mask layer is formed over the metal line. The spacer layer is formed over a top surface of the hard mask layer and over a sidewall of metal line. The second via structure is formed over the metal line through the spacer layer.
1 . A semiconductor structure, comprising:
a gate structure formed over a substrate;
source/drain epitaxial structures formed on opposite sides of the gate structure;
a contact structure formed over one of the source/drain epitaxial structures;
a first via structure formed over the contact structure;
a metal line electrically connected to the first via structure;
a hard mask layer formed over the metal line;
a spacer layer formed over a top surface of the hard mask layer and over a sidewall of metal line; and
a second via structure formed over the metal line through the spacer layer.
2 . The semiconductor structure as claimed in claim 1 , wherein the second via structure is in contact with the metal line through the hard mask layer.
3 . The semiconductor structure as claimed in claim 1 , wherein the top surface of the hard mask layer is curved.
4 . The semiconductor structure as claimed in claim 1 , wherein a bottom portion of the second via structure is surrounded by the hard mask layer.
5 . The semiconductor structure as claimed in claim 1 , wherein a bottom surface of the second via structure is level with a bottom surface of the hard mask layer.
6 . The semiconductor structure as claimed in claim 1 , wherein the spacer layer is curved over the source/drain epitaxial structures and is straight over the gate structure.
7 . The semiconductor structure as claimed in claim 1 , further comprising a glue layer disposed between the first via structure and the metal line and surrounded by the spacer layer.
8 . The semiconductor structure as claimed in claim 1 , wherein a sidewall of the second via structure is substantially aligned with a sidewall of the spacer layer.
9 . A semiconductor structure, comprising:
a source/drain contact structure formed over a substrate;
an inter-layer dielectric (ILD) structure covering a top surface of the source/drain contact structure;
a first via structure formed over the source/drain contact structure through the ILD structure;
a metal line formed over the first via structure;
a hard mask layer formed over the metal line;
a second via structure electrically connected to the metal line through the hard mask layer;
a spacer layer extending from a sidewall of the second via structure to the ILD structure; and
a dielectric layer formed over the spacer layer.
10 . The semiconductor structure as claimed in claim 9 , further comprising a glue layer disposed between the first via structure and the metal line.
11 . The semiconductor structure as claimed in claim 10 , wherein the spacer layer extends along a sidewall of the metal line and a sidewall of the glue layer.
12 . The semiconductor structure as claimed in claim 10 , wherein a sidewall of the hard mask layer, a sidewall of the metal line, and a sidewall of the glue layer is coplanar.
13 . The semiconductor structure as claimed in claim 9 , wherein a bottom surface of the second via structure is in contact with the dielectric layer.
14 . The semiconductor structure as claimed in claim 9 , wherein the spacer layer has a thickness in a range of about 30 Å to about 80 Å.
15 . The semiconductor structure as claimed in claim 9 , wherein the hard mask layer has a thickness in a range of about 80 Å to about 150 Å.
16 . A semiconductor structure, comprising:
a fin structure formed over a substrate;
a source/drain epitaxial structure formed over the fin structure;
a contact structure formed over the source/drain epitaxial structure;
a first via structure electrically connected to the contact structure;
a metal line electrically connected to the first via structure;
a second via structure electrically connected to the metal line;
a hard mask layer covering a top surface of the metal line and a bottom surface of the second via structure; and
a spacer layer covering a top surface of the hard mask layer and a sidewall of the second via structure.
17 . The semiconductor structure as claimed in claim 16 , wherein the hard mask layer has a thickness decreasing from the sidewall of the second via structure to an edge of the hard mask layer.
18 . The semiconductor structure as claimed in claim 16 , wherein the bottom surface of the second via structure is formed over the spacer layer.
19 . The semiconductor structure as claimed in claim 16 , wherein the spacer layer has a curved portion over the hard mask layer.
20 . The semiconductor structure as claimed in claim 16 , wherein the spacer layer includes SiN, SiC, or a combination thereof.