IP Library › Granted Patent US 12,542,982
Granted Patent B2
US 12,542,982 · App. 18/554,043 · Granted Feb 3, 2026

Imaging apparatus, electronic device, and signal processing method

Inventor: Daisuke Saito (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H04N25/77H04N25/10
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,542,982
App. No.
18/554,043
Granted
Feb 3, 2026
Kind
B2
Abstract

To provide an imaging apparatus which enables sophisticated calculations to be realized at lower power. An imaging apparatus according to an embodiment of the present disclosure includes: a first substrate group in which is arranged a light source cell array portion configured to generate a light signal; and a second substrate group in which is arranged a pixel array portion configured to photoelectrically convert the light signal and output a pixel signal representing a result of a sum-of-product computation. The first substrate group and the second substrate group are stacked so that at least a part of the light source cell array portion overlaps with the pixel array portion.

Claims (49)

1 . An imaging apparatus, comprising:

a first substrate group in which is arranged a light source cell array portion configured to generate a light signal,

wherein the light signal is visible light; and

a second substrate group in which is arranged a pixel array portion configured to photoelectrically convert the light signal and output a pixel signal representing a result of a sum-of-product computation,

wherein the first substrate group and the second substrate group are stacked so that at least a part of the light source cell array portion overlaps with the pixel array portion, and

wherein the sum-of-product computation includes sums of products of the photoelectrically converted light signal and a corresponding coefficient for each pixel.

2 . The imaging apparatus according to claim 1 , wherein

the light source cell array portion includes a plurality of light source cells arranged in a two-dimensional pattern,

the pixel array portion includes a plurality of pixels arranged in a two-dimensional pattern, and

in the plurality of light source cells and the plurality of pixels, a center pitch of one is an integral multiple of a center pitch of the other.

3 . The imaging apparatus according to claim 2 , wherein each of the plurality of light source cells includes a light-emitting element, an active element configured to independently control the light-emitting element, and a storage portion provided between the light-emitting element and the active element.

4 . The imaging apparatus according to claim 3 , wherein the storage portion is configured to store data related to the sum-of-product computation.

5 . The imaging apparatus according to claim 1 , wherein

the first substrate group includes:

a light source substrate on which the light source cell array portion is arranged; and

a light source control substrate which is stacked on top of the light source substrate and on which a light source control circuit configured to control drive of the light source cell array portion is arranged.

6 . The imaging apparatus according to claim 1 , wherein

the second substrate group includes:

a substrate on which the pixel array portion is arranged; and

a memory substrate which is stacked below the substrate and on which is arranged a memory cell array portion configured to output a convolution signal representing a result of a sum-of-product computation of an input signal based on the pixel signal.

7 . The imaging apparatus according to claim 6 , wherein at least one of the pixel signal and the convolution signal is an analog signal.

8 . The imaging apparatus according to claim 7 , further comprising a computing in memory (CIM) readout circuit configured to process the convolution signal read from the memory cell array portion.

9 . The imaging apparatus according to claim 7 , further comprising a pixel signal processing circuit configured to process the pixel signal read from the pixel array portion.

10 . The imaging apparatus according to claim 9 , wherein the pixel signal processing circuit is arranged on a same substrate as the pixel array portion.

11 . The imaging apparatus according to claim 9 , wherein the pixel signal processing circuit is arranged on a different substrate from the pixel array portion.

12 . The imaging apparatus according to claim 1 , wherein

the pixel array portion includes a photoelectric conversion portion configured to photoelectrically convert the light signal and a pixel transistor portion configured to subject the light signal to a sum-of-product computation, and

the photoelectric conversion portion is arranged on a different substrate from the pixel transistor portion.

13 . The imaging apparatus according to claim 1 , further comprising an optical modulation element arranged between the light source cell array portion and the pixel array portion.

14 . The imaging apparatus according to claim 1 , further comprising a shutter arranged between the light source cell array portion and the pixel array portion.

15 . The imaging apparatus according to claim 1 , further comprising a black mask provided on an edge of the first substrate group and an edge of the second substrate group.

16 . The imaging apparatus according to claim 1 , wherein the first substrate group and the second substrate group are housed in a light-shielding package.

17 . The imaging apparatus according to claim 1 , wherein the pixel array portion is configured to receive, in a direction opposite to the light signal, reflected light having been reflected by a subject.

18 . An electronic device, comprising:

an imaging apparatus including:

a first substrate group in which is arranged a light source cell array portion configured to generate a light signal,

wherein the light signal is visible light; and

a second substrate group in which is arranged a pixel array portion configured to photoelectrically convert the light signal and output a pixel signal representing a result of a sum-of-product computation,

wherein the first substrate group and the second substrate group are stacked so that at least a part of the light source cell array portion overlaps with the pixel array portion, and

wherein the sum-of-product computation includes sums of products of the photoelectrically converted light signal and a corresponding coefficient for each pixel.

19 . The electronic device according to claim 18 , wherein

the light source cell array portion includes a plurality of light source cells arranged in a two-dimensional pattern,

the pixel array portion includes a plurality of pixels arranged in a two-dimensional pattern, and

in the plurality of light source cells and the plurality of pixels, a center pitch of one is an integral multiple of a center pitch of the other.

20 . A signal processing method, comprising the steps of:

generating a light signal with a light source cell array portion arranged in a first substrate group,

wherein the light signal is visible light; and

photoelectrically converting the light signal and outputting a pixel signal representing a result of a sum-of-product computation with a pixel array portion which overlaps with at least a part of the light source cell array portion, and

wherein the sum-of-product computation includes sums of products of the photoelectrically converted light signal and a corresponding coefficient for each pixel.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2023
From: SAITO, DAISUKE
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 065133/0779 →
Priority Claims (1)
JP 2021-069851 · Apr 16, 2021 · national
Continuity (1)
Related Publication 20240121532A1 · Apr 11, 2024
References Cited (13)
US 11907832B2 · Shen · 2024 [cited by examiner]
US 12373366B2 · Chen · 2025 [cited by examiner]
US 20040195572A1 · Kato · 2004 [cited by examiner]
US 20190191111A1 · Juen et al. · 2019 [cited by applicant]
US 20200250533A1 · Shen · 2020 [cited by applicant]
US 20220094842A1 · Fujiwara · 2022 [cited by examiner]
US 20220291739A1 · Ko · 2022 [cited by examiner]
US 20230188865A1 · Hsieh · 2023 [cited by examiner]
JP H03204624A · 1991 [cited by applicant]
JP 2020113809 · 2020 [cited by applicant]
WO WO2018037862 · 2018 [cited by applicant]
WO WO2020145142A1 · 2020 [cited by applicant]
International Search Report and Written Opinion prepared by the Japan Patent Office on Apr. 12, 2022, for International Application No. PCT/JP2022/007073, 2 pgs. [cited by applicant]