IP Library › Granted Patent US 12,543,512
Granted Patent B2
US 12,543,512 · App. 17/717,611 · Granted Feb 3, 2026

Semiconductor device and semiconductor apparatus including the same

Inventors: Wooyoung Yang (Suwon-si, KR); Segab Kwon (Seoul, KR); Hajun Sung (Hwaseong-si, KR); Dongho Ahn (Hwaseong-si, KR); Changseung Lee (Yongin-si, KR); Minwoo Choi (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10N70/231H10B63/84H10N70/826H10N70/8822H10N70/8825H10N70/8828H10N70/8833
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Quick Facts
Patent No.
US 12,543,512
App. No.
17/717,611
Granted
Feb 3, 2026
Kind
B2
Abstract

Provided are a semiconductor device and a semiconductor apparatus. The semiconductor device may include a first electrode; a second electrode spaced apart from the first electrode; and a selection device layer including a chalcogen compound layer between the first electrode and the second electrode and a metal oxide doped in the chalcogen compound layer. In the semiconductor device, by doping the metal oxide, an off-current value (leakage current value) of the selection device layer may be reduced, and static switching characteristics may be implemented.

Claims (70)

1 . A semiconductor device comprising:

a first electrode;

a second electrode spaced apart from the first electrode; and

a selection device layer including a chalcogen compound layer between the first electrode and the second electrode and a metal oxide doped in the chalcogen compound layer, wherein the metal oxide is intercalated into the chalcogen compound layer in a layered structure, and the layered structure includes a first selection device layer and a second selection device layer extending between the first electrode and the second electrode in a direction parallel to a surface of the first electrode facing a surface of the second electrode,

wherein the metal oxide includes a compound represented by Formula 1 below,

MO x   [Formula 1]

wherein, in Formula 1, M is a group 2 element, a group 3 element, a group 4 element other than Zr and Hf, a group 5 element, a group 13 element other than Al, a group 14 element other than Si, or a group 15 element, and

0.5≤x≤3.

2 . The semiconductor device of claim 1 , wherein

in Formula 1, M is Ga, In, Ge, Sn, As, Sb, Sc, Sr, Ba, Ti, V, Nb, T, Mg, or a combination thereof, and

the first selection device layer includes the chalcogen compound layer without the metal oxide, and the metal oxide is doped in the second selection device layer.

3 . The semiconductor device of claim 1 , wherein, in the metal oxide, a metal element of the metal oxide is included in an amount ranging from about 1 at % to about 30 at % with respect to total elements of the selection device layer.

4 . The semiconductor device of claim 1 , wherein the metal oxide is doped in a complete solid solution state in the chalcogen compound layer.

5 . The semiconductor device of claim 1 , wherein the metal oxide is intercalated into the chalcogen compound layer in a layered structure.

6 . The semiconductor device of claim 5 , wherein the metal oxide is intercalated in a single-layer or multi-layer structure into the chalcogen compound layer.

7 . The semiconductor device of claim 5 , wherein, in the layered structure, a total thickness of layers doped with the metal oxide is in a range of about 0.05 nm to about 30 nm.

8 . The semiconductor device of claim 1 , wherein the chalcogen compound layer includes:

at least one first element selected from germanium (Ge) and tin (Sn), and

at least one second element selected from sulfur(S), selenium (Se), and tellurium (Te).

9 . The semiconductor device of claim 1 , wherein the chalcogen compound layer further includes at least one third element selected from arsenic (As), antimony (Sb), silicon (Si), and bismuth (Bi).

10 . The semiconductor device of claim 1 , wherein the chalcogen compound layer further includes at least one fourth element selected from boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and indium (In).

11 . The semiconductor device of claim 1 , wherein the chalcogen compound layer further includes at least one fifth element selected from carbon (C), nitrogen (N), oxygen (O), phosphorus (P), and sulfur(S).

12 . The semiconductor device of claim 1 , wherein the chalcogen compound layer includes at least one of compounds represented by Formulas 2 to 5 below:

A a B b C c   [Formula 2]

A a B b C c D d   [Formula 3]

A a B b   [Formula 4]

A a B b C c E e   [Formula 5]

wherein, in Formula 2, 3, 4 or 5,

A is a first element,

B is a second element,

C is a third element,

D is a fourth element, and

E is a fifth element, and

in Formula 2, a+b+c=1,

in Formula 3, a+b+c+d=1,

in Formula 4, a+b=1, and

in Formula 5, a+b+c+e=1.

13 . The semiconductor device of claim 1 , wherein one or more of elements included in the chalcogen compound layer each independently has a concentration gradient in a thickness direction of the selection device layer.

14 . The semiconductor device of claim 1 , wherein,

the metal oxide is doped in some layers of the chalcogen compound layer to provide a layered structure, the selection device layer includes two or more chalcogen compound layers having different compositions from each other, and

the two or more chalcogen compound layers having different compositions from each other include a first selection device layer and a second selection device layer extending between the first electrode and the second electrode in a direction parallel to a surface of the first electrode facing a surface of the second electrode,

the first selection device layer includes the chalcogen compound layer without the metal oxide, and

the metal oxide is doped in the second selection device layer.

15 . The semiconductor device of claim 1 , wherein the chalcogen compound layer has a thickness of about 0.5 nm to about 30.0 nm.

16 . The semiconductor device of claim 1 , wherein the chalcogen compound layer has ovonic threshold switching characteristics.

17 . The semiconductor device of claim 1 , wherein the semiconductor device has a lower leakage current than a semiconductor device including a chalcogen compound layer not doped with the metal oxide.

18 . The semiconductor device of claim 1 , further comprising:

a variable resistance layer,

wherein the selection device layer is electrically connected to the variable resistance layer.

19 . The semiconductor device of claim 18 , further comprising:

a third electrode,

wherein the selection device layer is between the first electrode and the second electrode, and

the variable resistance layer is between the second electrode and the third electrode.

20 . A semiconductor apparatus, comprising:

a semiconductor device, and the semiconductor device comprising:

a first electrode;

a second electrode spaced apart from the first electrode; and

a selection device layer including a chalcogen compound layer between the first electrode and the second electrode and a metal oxide doped in the chalcogen compound layer, wherein the metal oxide is intercalated into the chalcogen compound layer in a layered structure,

and the layered structure includes a first selection device layer and a second selection device layer extending between the first electrode and the second electrode in a direction parallel to a surface of the first electrode facing a surface of the second electrode, wherein the metal oxide includes a compound represented by Formula 1 below,

MO x   [Formula 1]

wherein, in Formula 1, M is a group 2 element, a group 3 element, a group 4 element other than Zr and Hf, a group 5 element, a group 13 element other than Al, a group 14 element other than Si, or a group 15 element, and

0.5≤x≤3.

21 . The semiconductor apparatus of claim 20 , comprising:

a plurality of first electrode lines on a substrate, parallel to an upper surface of the substrate, and extending in a first direction; and

a plurality of second electrode lines on the plurality of first electrode lines, parallel to the upper surface of the substrate, and extending in a second direction that is different from the first direction, wherein

the semiconductor device is between the plurality of first electrode lines and the plurality of second electrode lines at a crossing point thereof.

22 . The semiconductor apparatus of claim 21 , further comprising:

a plurality of third electrode lines on the plurality of first and second electrode lines and extending in the first direction; and

a second semiconductor device arranged between the plurality of second electrode lines and the plurality of third electrode lines and at a crossing point thereof, wherein

the second semiconductor device and the semiconductor device have a same structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2022
From: YANG, WOOYOUNG; KWON, SEGAB; SUNG, HAJUN; AHN, DONGHO; LEE, CHANGSEUNG; CHOI, MINWOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 059585/0216 →
Priority Claims (1)
KR 10-2021-0125211 · Sep 17, 2021 · national
Continuity (1)
Related Publication 20230088249A1 · Mar 23, 2023
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