IP Library › Granted Patent US 12,543,612
Granted Patent B2
US 12,543,612 · App. 18/151,743 · Granted Feb 3, 2026

Semiconductor devices and methods of forming the same

Inventors: Chao-Wei Chiu (Hsinchu, TW); Jen-Jui Yu (Taipei, TW); Hsuan-Ting Kuo (Taichung, TW); Cheng-Shiuan Wong (Hsinchu, TW); Hsiu-Jen Lin (Zhubei, TW); Ching-Hua Hsieh (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L24/13H01L21/4853H01L23/49816H01L24/11H01L25/0652H01L25/0655H01L23/3675H01L23/49833H01L24/05H01L24/29H01L24/32H01L2224/05624H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/05664H01L2224/11849H01L2224/13111H01L2224/13113H01L2224/13117H01L2224/13139H01L2224/13147H01L2224/13155H01L2224/29193H01L2224/2929H01L2224/29324H01L2224/29339H01L2224/29347H01L2224/29386H01L2224/32245H01L2924/01032H01L2924/014H01L2924/0503H01L2924/05032H01L2924/0543
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Quick Facts
Patent No.
US 12,543,612
App. No.
18/151,743
Granted
Feb 3, 2026
Kind
B2
Abstract

Semiconductor devices including the use of solder materials and methods of manufacturing are provided. In embodiments the solder materials utilize a first tensile raising material, a second tensile raising material, and a eutectic modifier material. By utilizing the materials a solder material can be formed and used with a reduced presence of needles that may otherwise form during the placement and use of the solder material.

Claims (38)

1 . A method of manufacturing a semiconductor device, the method comprising:

applying an external connector to a substrate, the external connector comprising:

a first tensile raising material at a first percentage of between about 2.2% and less than 2.8%;

a second tensile raising material at a second percentage of between about 4% and about 4.4%; and

a eutectic modifier at a third percentage of between about 0.5% and about 1.1%; and

reflowing the external connector, wherein after the reflowing the external connector, the external connector is free from silver-based intermetallic compound needles.

2 . The method of claim 1 , wherein the first tensile raising material comprises silver, the second tensile raising material comprises bismuth, and the eutectic modifier comprises copper.

3 . The method of claim 1 , wherein the substrate is part of a fan-out package.

4 . The method of claim 1 , wherein the substrate is part of a wafer level chip scale package.

5 . The method of claim 1 , wherein the substrate is part of an integrated fan out on substrate structure.

6 . The method of claim 1 , wherein the substrate is part of a chip on wafer on substrate.

7 . The method of claim 1 , wherein the external connector further comprises:

nickel; and

germanium.

8 . A method of manufacturing a semiconductor device, the method comprising:

placing a solder material onto a substrate, the solder material having a composition of silver between about 2.2% and about 2.8%;

heating the solder material past a eutectic temperature; and

cooling the solder material from a solidus start temperature to a solidus end temperature, wherein a difference between the solidus start temperature and the solidus end temperature is at least 13° C., wherein after the cooling the solder material the solder material is free from silver-based intermetallic compound needles.

9 . The method of claim 8 , wherein the solder material has a composition of bismuth between about 4% and about 4.4%.

10 . The method of claim 9 , wherein the solder material has a composition of copper between about 0.5% and about 1.1%.

11 . The method of claim 8 , wherein after the cooling the solder material the solder material has a tensile strength of about 96.7 MPa.

12 . The method of claim 11 , wherein after the cooling the solder material the solder material has an elongation of about 39%.

13 . The method of claim 8 , wherein the substrate is part of a flip chip chip scale package.

14 . The method of claim 8 , wherein the substrate is part of a chip on wafer on substrate.

15 . A semiconductor device comprising:

a first semiconductor die and a second semiconductor die encased within an encapsulant;

an interposer substrate bonded to the first semiconductor die and the second semiconductor die;

a substrate bonded to the interposer substrate; and

an external connection on the substrate, the external connection comprising:

tin;

silver at a concentration of between about 2.2% and less than 2.8%;

bismuth at a concentration of between about 4% and about 4.4%; and

copper at a concentration of between about 0.5% and about 1.1%.

16 . The semiconductor device of claim 15 , wherein the external connection has a tensile strength of about 96.7 MPa.

17 . The semiconductor device of claim 15 , wherein the external connection has an elongation of about 39%.

18 . The semiconductor device of claim 15 , wherein the external connection further comprises nickel.

19 . The semiconductor device of claim 15 , wherein the external connection further comprises germanium.

20 . The semiconductor device of claim 15 , wherein the external connection is free from silver-based needles.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2023
From: CHIU, CHAO-WEI; YU, JEN-JUI; KUO, HSUAN-TING; WONG, CHENG-SHIUAN; LIN, HSIU-JEN; HSIEH, CHING-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 062313/0987 →
Continuity (2)
Provisional Application 63385815 · Dec 2, 2022
Related Publication 20240186275A1 · Jun 6, 2024
References Cited (4)
US 20100307823A1 · Kawamata · 2010 [cited by examiner]
US 20210193605A1 · Tseng · 2021 [cited by examiner]
US 20220037231A1 · Hsiao et al. · 2022 [cited by applicant]
TW 201431025A · 2014 [cited by applicant]