Semiconductor structure and manufacturing method thereof
View Patent ↗A method includes forming a semiconductor fin upwardly extending from a substrate; forming a gate strip extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and at opposite sides of the gate strip; forming a gate spacer on a sidewall of the gate strip; forming a film layer on the gate spacer; performing an etching process on the gate strip to break the gate strip into a first gate structure and a second gate structure, the etching process further consuming the gate spacer while remains the film layer; forming an isolation structure interposing the first and second gate structures.
1 . A method, comprising:
forming a semiconductor fin upwardly extending from a substrate;
forming a gate strip extending across the semiconductor fin;
forming source/drain regions on the semiconductor fin and at opposite sides of the gate strip;
forming a gate spacer on a sidewall of the gate strip;
forming a film layer on the gate spacer;
performing an etching process on the gate strip to break the gate strip into a first gate structure and a second gate structure, the etching process further consuming the gate spacer while remains the film layer; and
forming an isolation structure interposing the first and second gate structures.
2 . The method of claim 1 , wherein the film layer is made of a silicon-containing material.
3 . The method of claim 1 , wherein the film layer has a lower nitrogen atomic concentration than the gate spacer.
4 . The method of claim 1 , further comprising:
depositing an interlayer dielectric (ILD) layer laterally surrounding the gate strip, wherein the film layer has a different silicon atomic concentration than the ILD layer.
5 . The method of claim 1 , further comprising:
depositing an interlayer dielectric (ILD) layer laterally surrounding the gate strip, wherein the film layer has a different density than the ILD layer.
6 . The method of claim 1 , wherein forming the film layer is performed by using a furnace.
7 . The method of claim 1 , further comprising implanting a dopant into the film layer.
8 . The method of claim 1 , wherein the film layer is made of silicon oxide doped with germanium, nitrogen, phosphorus, or boron.
9 . The method of claim 1 , wherein the isolation structure has a dielectric constant less than about 5.
10 . The method of claim 1 , wherein the isolation structure is made of SiOC.
11 . A method, comprising:
forming first and second semiconductive channel patterns on a substrate;
forming a gate pattern extending across the first and second semiconductive channel patterns;
forming first source/drain patterns on the first semiconductive channel pattern and at opposite sides of the gate pattern and forming second source/drain patterns on the second semiconductive channel pattern and at opposite sides of the gate pattern;
forming a first spacer layer on a sidewall of the gate pattern;
selectively forming a leakage barrier on the first spacer layer;
impaling a dopant into the leakage barrier;
patterning the gate pattern to form a first gate structure extending across the first semiconductive channel pattern and a second gate structure extending across the second semiconductive channel pattern; and
depositing a dielectric material over the substrate and in contact with a longitudinal end of the first gate structure and a longitudinal end of the second gate structure.
12 . The method of claim 11 , wherein the leakage barrier has a lower nitrogen atomic concentration than the first spacer layer.
13 . The method of claim 11 , wherein the first spacer layer is dopant-free.
14 . The method of claim 11 , wherein the dielectric material is made of silicon oxy-carbo-nitride.
15 . The method of claim 11 , further comprising:
forming a second spacer layer on the sidewall of the gate pattern prior to forming the first spacer layer, the second spacer layer having a higher oxygen atomic concentration than the first spacer layer.
16 . A semiconductor structure, comprising:
a semiconductor substrate;
a nanostructured pedestal on the semiconductor substrate and having a top surface and opposite side surfaces;
a gate strip wrapping around the top surface and the opposite side surfaces of the nanostructured pedestal;
epitaxial structures on the nanostructured pedestal and at opposite sides of the gate strip;
an isolation structure abutting a longitudinal end of the gate strip and forming a linear boundary with the gate strip, wherein the isolation structure has a rectangular profile from a top view and a trapezoidal profile from a cross-sectional view;
a spacer lining a sidewall of the gate strip;
a first doped silicon oxide leakage barrier lining a sidewall of the spacer opposite to the gate strip, wherein the first doped silicon oxide leakage barrier comprises an implanted dopant; and
a second doped silicon oxide leakage barrier lining a sidewall of the isolation structure.
17 . The semiconductor structure of claim 16 , wherein the second doped silicon oxide leakage barrier is in contact with the isolation structure.
18 . The semiconductor structure of claim 16 , wherein the second doped silicon oxide leakage barrier has a lower nitrogen atomic concentration than the spacer.
19 . The semiconductor structure of claim 16 , wherein the isolation structure has an upper portion having a narrower width than a lower portion of the isolation structure from the cross-sectional view.
20 . The semiconductor structure of claim 16 , wherein the first doped silicon oxide leakage barrier is doped with germanium, nitrogen, phosphorus, or boron.