Semiconductor devices with backside via and methods thereof
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.
1 . A semiconductor structure, comprising:
a first source/drain feature and a second source/drain feature over a substrate;
a dielectric structure over the first and second source/drain features;
an isolation feature extending through dielectric structure and disposed directly on the first source/drain feature, and
a source/drain contact extending through the dielectric structure to couple to the second source/drain feature,
wherein, when viewed from top, the isolation feature spans a first width, and the source/drain contact spans a second width less than the first width.
2 . The semiconductor structure of claim 1 , wherein, when viewed from top, the isolation feature and the source/drain contact extend lengthwise along a same direction.
3 . The semiconductor structure of claim 1 , wherein, in a layout view, the first source/drain feature spans a third width, the third width is less than the first width.
4 . The semiconductor structure of claim 1 , further comprising: a source/drain via disposed under and electrically coupled to the first source/drain feature.
5 . The semiconductor structure of claim 4 , wherein, in a layout view, the source/drain via spans a third width, the third width is less than the first width.
6 . The semiconductor structure of claim 4 , further comprising: a dielectric liner extending along a sidewall surface of the source/drain via.
7 . The semiconductor structure of claim 1 , wherein the isolation feature covers an entirety of a top surface of the first source/drain feature.
8 . The semiconductor structure of claim 1 , further comprising:
a gate structure disposed between the isolation feature and the source/drain contact; and
a via electrically coupled to the gate structure,
wherein, in a layout view, a distance between the via and the isolation feature is less than a distance between the via and the source/drain contact.
9 . A semiconductor structure, comprising:
a source/drain feature over a substrate;
a dielectric structure over the source/drain feature;
a dielectric feature extending through the dielectric structure and over the source/drain feature;
a gate structure over the substrate;
a gate spacer disposed laterally between the gate structure and the dielectric feature; and
a conductive via under the source/drain feature,
wherein, in a layout view, the dielectric feature is wider than the conductive via.
10 . The semiconductor structure of claim 9 , wherein the dielectric structure comprises:
an etch stop layer over the source/drain feature; and
an interlayer dielectric layer on the etch stop layer.
11 . The semiconductor structure of claim 9 , wherein a top surface of the dielectric feature is above a top surface of the dielectric structure.
12 . The semiconductor structure of claim 9 , wherein the dielectric feature has a first portion embedded in the dielectric structure and a second portion over the dielectric structure, the second portion spans a width greater than the first portion.
13 . The semiconductor structure of claim 9 , wherein the dielectric feature covers an entirety of a top surface of the source/drain feature.
14 . The semiconductor structure of claim 9 , wherein the source/drain feature is a first source/drain feature, and the semiconductor structure further comprises:
a channel region coupled to the first source/drain feature;
a second source/drain feature coupled to the channel region; and
a source/drain contact extending through the dielectric structure and over the second source/drain feature.
15 . The semiconductor structure of claim 14 , wherein the source/drain contact spans a width less than the dielectric feature.
16 . A semiconductor structure, comprising:
a plurality of nanostructures over a substrate;
a gate structure disposed over and wrapping around each of the plurality of nanostructures;
a gate spacer extending along a sidewall of the gate structure;
a source/drain feature coupled to the plurality of nanostructures;
a conductive feature disposed under and electrically coupled to the source/drain feature; and
a gate via vertically overlapped with and electrically coupled to the gate structure, wherein a center line of the gate via is offset from a center line of the gate structure.
17 . The semiconductor structure of claim 16 , wherein the source/drain feature is a first source/drain feature, and the semiconductor structure further comprises:
a second source/drain feature coupled to the plurality of nanostructures;
a dielectric structure over the substrate; and
a source/drain contact extending through the dielectric structure to couple to the second source/drain feature; and
an isolation feature extending through the dielectric structure to contact the first source/drain feature.
18 . The semiconductor structure of claim 17 , wherein a top surface of the isolation feature is above a top surface of the source/drain contact.
19 . The semiconductor structure of claim 17 , wherein a distance between the gate via and the source/drain contact is greater than a distance between the gate via and the isolation feature.
20 . The semiconductor structure of claim 17 , wherein the conductive feature spans a first width, and the isolation feature spans a second width greater than the first width.