IP Library › Granted Patent US 12,557,303
Granted Patent B2
US 12,557,303 · App. 18/743,906 · Granted Feb 17, 2026

Capacitor structure and method for manufacturing the same

Inventors: Teng-Chuan Hu (Tainan, TW); Chu-Fu Lin (Kaohsiung, TW); Chun-Hung Chen (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10D1/042H10D1/716
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Quick Facts
Patent No.
US 12,557,303
App. No.
18/743,906
Granted
Feb 17, 2026
Kind
B2
Abstract

A capacitor structure comprises a substrate having a first side and a second side opposite to the first side; a plurality of first trenches formed on the first side of the substrate; a plurality of second trenches formed on the second side of the substrate; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches, wherein a first depth of each of the first trenches or a second depth of each of the second trenches is greater than half of a thickness of the substrate.

Claims (42)

1 . A capacitor structure, comprising:

a substrate having a first side and a second side opposite to the first side;

a plurality of first trenches formed on the first side of the substrate;

a plurality of second trenches formed on the second side of the substrate;

a first capacitor extending along the first side and into the first trenches; and

a second capacitor extending along the second side and into the second trenches, wherein a first depth of each of the first trenches or a second depth of each of the second trenches is greater than half of a thickness of the substrate, and the first trenches and the second trenches correspond to an array of holes in a top view.

2 . The capacitor structure according to claim 1 , wherein the substrate has an upper surface corresponding to the first side of the substrate,

wherein the first trenches are disposed along a first direction and a second direction on the first side of the substrate, the first direction and the second direction are intersected with each other and parallel to the upper surface of the substrate,

wherein the first trenches penetrate the substrate along a third direction intersected with the first direction and the second direction, and the second trenches penetrate the substrate along the third direction.

3 . The capacitor structure according to claim 2 , wherein the first trenches and the second trenches are overlapped in the first direction.

4 . The capacitor structure according to claim 3 , wherein the first trenches and the second trenches are separated in the third direction.

5 . The capacitor structure according to claim 3 , wherein the first trenches are disposed in a first region on the first side of the substrate, the second trenches are disposed in a second region on the second side of the substrate, and the first region and the second region are overlapped in the third direction.

6 . The capacitor structure according to claim 3 , wherein the first trenches are disposed in a first region on the first side of the substrate, the second trenches are disposed in a second region on the second side of the substrate, and the first region and the second region are separated from each other in the third direction.

7 . The capacitor structure according to claim 2 , further comprising a first via and a second via penetrating through the substrate, respectively,

wherein the first capacitor and the second capacitor are electrically connected to each other through the first via and the second via.

8 . The capacitor structure according to claim 7 , wherein the first capacitor comprises a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer and a third conductive layer sequentially stacked on the first side of the substrate, the second capacitor comprises a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer and a third conductive layer sequentially stacked on the second side of the substrate,

wherein the first conductive layer of the first capacitor, the first conductive layer of the second capacitor, the third conductive layer of the first capacitor and the third conductive layer of the second capacitor are electrically connected to the first via; the second conductive layer of the first capacitor and the second conductive layer of the second capacitor are electrically connected to the second via.

9 . The capacitor structure according to claim 7 , wherein the first capacitor comprises a first conductive layer, a first dielectric layer and a second conductive layer sequentially stacked on the first side of the substrate, the second capacitor comprises a first conductive layer, a first dielectric layer and a second conductive layer sequentially stacked on the second side of the substrate,

wherein the first conductive layer of the first capacitor and the first conductive layer of the second capacitor are electrically connected to the first via; the second conductive layer of the first capacitor and the second conductive layer of the second capacitor are electrically connected to the second via.

10 . A method for manufacturing a capacitor structure:

providing a substrate having a first side and a second side opposite to the first side;

forming a plurality of first trenches on the first side;

forming a first capacitor extending along the first side and into the first trenches;

forming a plurality of second trenches on the second side; and

forming a second capacitor extending along the second side and into the second trenches, wherein a first depth of each of the first trenches or a second depth of each of the second trenches is greater than half of a thickness of the substrate, and the first trenches and the second trenches correspond to an array of holes in a top view.

11 . The method according to claim 10 , wherein the substrate has an upper surface corresponding to the first side of the substrate,

wherein the first trenches are disposed along a first direction and a second direction on the first side of the substrate, the first direction and the second direction are intersected with each other and parallel to the upper surface of the substrate,

wherein the first trenches penetrate the substrate along a third direction intersected with the first direction and the second direction, and the second trenches penetrate the substrate along the third direction.

12 . The method according to claim 11 , wherein the first trenches and the second trenches are overlapped in the first direction.

13 . The method according to claim 12 , wherein the first trenches and the second trenches are separated in the third direction.

14 . The method according to claim 11 , wherein the first trenches are disposed in a first region on the first side of the substrate, the second trenches are disposed in a second region on the second side of the substrate, and the first region and the second region are overlapped in the third direction.

15 . The method according to claim 11 , wherein the first trenches are disposed in a first region on the first side of the substrate, the second trenches are disposed in a second region on the second side of the substrate, and the first region and the second region are separated from each other in the third direction.

16 . The method according to claim 10 , further comprising forming a first via and a second via penetrating through the substrate, respectively,

wherein the first capacitor and the second capacitor are electrically connected to each other through the first via and the second via.

17 . The method according to claim 16 , wherein:

forming the first capacitor comprises forming a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer and a third conductive layer sequentially stacked on the first side of the substrate;

forming the second capacitor comprises forming a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer and a third conductive layer sequentially stacked on the second side of the substrate;

wherein the first conductive layer of the first capacitor, the first conductive layer of the second capacitor, the third conductive layer of the first capacitor and the third conductive layer of the second capacitor are electrically connected to the first via; the second conductive layer of the first capacitor and the second conductive layer of the second capacitor are electrically connected to the second via.

18 . The method according to claim 16 , wherein:

forming the first capacitor comprises forming a first conductive layer, a first dielectric layer and a second conductive layer sequentially stacked on the first side of the substrate;

forming the second capacitor comprises forming a first conductive layer, a first dielectric layer and a second conductive layer sequentially stacked on the second side of the substrate;

wherein the first conductive layer of the first capacitor and the first conductive layer of the second capacitor are electrically connected to the first via; the second conductive layer of the first capacitor and the second conductive layer of the second capacitor are electrically connected to the second via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2024
From: HU, TENG-CHUAN; LIN, CHU-FU; CHEN, CHUN-HUNG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 067733/0269 →
Continuity (3)
Continuation 18119009 · Mar 8, 2023
Continuation 17136075 · Dec 29, 2020
Related Publication 20240332351A1 · Oct 3, 2024
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