High-K dielectric materials with dipole layer
A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.
1 . A method of forming a semiconductor device, comprising:
forming a first transistor comprising a first gate stack in a first region of a semiconductor substrate by at least:
forming an interfacial layer on the semiconductor substrate;
forming a first dielectric layer on the interfacial layer, the first dielectric layer having a first thickness and comprising praseodymium oxide;
forming a first dipole layer on the first dielectric layer;
forming a second dielectric layer on the first dipole layer; and
forming a first conductive work function layer on the second dielectric layer; and
forming a second transistor comprising a second gate stack in a second region of a semiconductor substrate by at least:
forming a third dielectric layer on the interfacial layer, the third dielectric layer having a second thickness and comprising praseodymium oxide;
forming a second dipole layer on the third dielectric layer, while forming the first dipole layer;
annealing, at a temperature ranging from 1050° C. to 1200° C., to drive dipole inducing elements from the second dipole layer into the third dielectric layer including the praseodymium oxide to the interfacial layer;
after annealing, removing residual second dipole layer by etching the residual second dipole layer;
after removing the residual second dipole layer, forming a fourth dielectric layer on the third dielectric layer, while forming the second dielectric layer, wherein the fourth dielectric layer comprises praseodymium oxide; and
forming a second conductive work function layer on the fourth dielectric layer, while forming the first conductive work function layer;
forming a gate electrode layer over the first conductive work function layer and second conductive work function layer;
wherein the first thickness is less than the second thickness;
wherein the first transistor is characterized by a first threshold voltage determined by dipole inducing elements in the first dipole layer on the first dielectric layer, and the second transistor is characterized by a second threshold voltage determined by dipole inducing elements on the interfacial layer;
wherein the first dielectric layer comprising praseodymium oxide remains substantially amorphous after the annealing.
2 . The method of claim 1 , wherein the first transistor is characterized by a first equivalent oxide thickness (EOT) and the second transistor is characterized by a second EOT, and the first EOT is less than or equal to the second EOT.
3 . The method of claim 1 , wherein the temperature is between 1050° C. and 1100° C.
4 . The method of claim 1 , wherein forming the first dielectric layer comprises performing a first number of atomic layer deposition (ALD) cycles, and wherein forming the third dielectric layer comprises performing a second number atomic layer deposition (ALD) cycle, wherein the first and second numbers are different.
5 . The method of claim 1 , wherein the first dielectric layer comprises a material which, in response to a 1 V potential, experiences a leakage current density less than 10 −8 A/cm 2 , when having an equivalent oxide thickness (EOT)=1.4 nm after being exposed to the temperature for about 15 s.
6 . A method of forming a semiconductor device, the method comprising:
forming a transistor comprising a gate stack on a semiconductor substrate by at least:
forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer comprises praseodymium oxide;
forming a dipole layer on the dielectric layer;
annealing, at a temperature ranging from 1050° C. to 1200° C., to drive dipole inducing elements from the dipole layer into the first dielectric layer including the praseodymium oxide;
after annealing, removing the dipole layer by etching the dipole layer;
after removing the dipole layer, forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises praseodymium oxide;
forming a conductive work function layer on the second dielectric layer;
forming a gate electrode layer on the conductive work function layer; and
varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor;
wherein the first dielectric layer comprising praseodymium oxide remains substantially amorphous after the annealing.
7 . The method of claim 6 , wherein the temperature is between 1050° C. and 1100° C.
8 . The method of claim 6 , wherein the first dielectric layer has a bandgap energy of greater than 5.3 eV.
9 . The method of claim 6 , wherein the dipole layer comprises aluminum oxide.
10 . The method of claim 6 , wherein the first dielectric layer comprises a material which, in response to a 1 V potential, experiences a leakage current density less than 10 −8 A/cm 2 , when having an equivalent oxide thickness (EOT)=1.4 nm after being exposed to the temperature for about 15 s.
11 . The method of claim 6 , wherein the transistor is characterized by a threshold voltage determined at least partly by a distance between dipole inducing elements in the dipole layer on the first dielectric layer and a surface of the semiconductor substrate.
12 . A method of forming a semiconductor device, comprising:
forming an interfacial layer on a semiconductor substrate comprising a first region and a second region;
forming a first dielectric layer having a first thickness on the interfacial layer in the first region, wherein the first dielectric layer comprises praseodymium oxide;
forming a third dielectric layer having a second thickness on the interfacial layer in the second region, wherein the third dielectric layer comprises praseodymium oxide, wherein the second thickness is larger than the first thickness;
forming a dipole layer on the first dielectric layer and the third dielectric layer;
annealing, at a temperature ranging from 1050° C. to 1200° C., to drive dipole inducing elements from the dipole layer into the first dielectric layer including the praseodymium oxide and the third dielectric layer;
after annealing, removing the dipole layer by etching the dipole layer;
after removing the dipole layer, forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises praseodymium oxide;
forming a conductive work function layer on the second dielectric layer, wherein a first gate stack of a first transistor disposed in the first region comprises the interfacial layer, the first dielectric layer, and the second dielectric layer, and wherein a second gate stack of a second transistor disposed in the second region comprises the interfacial layer, the third dielectric layer, and the second dielectric layer;
varying a first distance between dipole inducing elements in the dipole layer and a bottom surface of the interfacial layer by tuning the first thickness to adjust a first threshold voltage of the second transistor; and
varying a second distance between the dipole inducing elements in the dipole layer and the bottom surface of the interfacial layer by tuning the second thickness to adjust a second threshold voltage of the second transistor;
wherein the first dielectric layer comprising praseodymium oxide remains substantially amorphous after the annealing.
13 . The method of claim 12 , wherein the first transistor is characterized by a first equivalent oxide thickness (EOT) and the second transistor is characterized by a second EOT, and the first EOT is less than or equal to the second EOT.
14 . The method of claim 12 , wherein the temperature is between 1050° C. and 1100° C.
15 . The method of claim 12 , wherein forming the third dielectric layer comprising:
forming a first portion of the third dielectric layer while forming the first dielectric layer; and
forming a second portion of the third dielectric layer after forming the first dielectric layer.
16 . The method of claim 15 , wherein the first portion of the third dielectric layer has the first thickness.
17 . The method of claim 16 , wherein the second portion of the third dielectric layer has a thickness equal to a difference between the second thickness and the first thickness.
18 . The method of claim 1 , further comprising:
after etching the residual second dipole layer, forming a sacrificial layer on the third dielectric layer.
19 . The method of claim 18 , wherein the sacrificial layer comprises a material that reacts with the dipole-inducing elements.