IP Library Granted Patent US 12,557,698
Granted Patent B2
US 12,557,698 · App. 17/872,007 · Granted Feb 17, 2026

Package and manufacturing method thereof

Inventors: Der-Chyang Yeh (Hsin-Chu, TW); Sung-Feng Yeh (Taipei, TW); Jian-Wei Hong (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L25/0657H01L21/56H01L24/19H01L24/24H01L24/80H01L25/043H01L25/074H01L25/0756H01L2224/24011H01L2224/80895
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Quick Facts
Patent No.
US 12,557,698
App. No.
17/872,007
Granted
Feb 17, 2026
Kind
B2
Abstract

A manufacturing method of a package is provided. The method includes the following steps. A wafer substrate having first bonding pads is provided. A die is placed on the wafer substrate, wherein the die comprises second bonding pads bonded to the first bonding pads. The die is encapsulated by an etch stop layer and a first encapsulant. A redistribution structure is disposed over the die, the etch stop layer and the first encapsulant. A portion of the redistribution structure is removed to expose the first encapsulant. The first encapsulant is removed to expose the etch stop layer. A dielectric structure is disposed over the exposed etch stop layer and laterally encapsulates the die and the redistribution structure.

Claims (51)

1 . A manufacturing method of a package, comprising:

providing a wafer substrate having first bonding pads;

placing a die on the wafer substrate, wherein the die comprises second bonding pads bonded to the first bonding pads;

encapsulating the die by an etch stop layer and a first encapsulant;

forming a redistribution structure over the die, the etch stop layer and the first encapsulant;

removing a portion of the redistribution structure to expose the first encapsulant;

removing the first encapsulant to expose the etch stop layer; and

forming a dielectric structure over the exposed etch stop layer and laterally encapsulating the die and the redistribution structure.

2 . The method of claim 1 , wherein the portion of the redistribution structure is removed by performing a dry etching process.

3 . The method of claim 1 , wherein the first encapsulant is removed by performing a wet etching process.

4 . The method of claim 1 , further comprising:

forming conductive pads over the redistribution structure; and

forming conductive terminals over the conductive pads.

5 . The method of claim 4 , wherein the dielectric structure comprises a passivation layer over the redistribution structure and the conductive pads, and in contact with the conductive terminals.

6 . The method of claim 5 , wherein the conductive pads are formed before the portion of the redistribution structure is removed.

7 . The method of claim 4 , wherein the dielectric structure comprises a second encapsulant, and a material of the second encapsulant is different from a material of the first encapsulant.

8 . The method of claim 7 , wherein the second encapsulant is formed by a molding process.

9 . The method of claim 7 , wherein the conductive pads are formed after the portion of the redistribution structure is removed.

10 . The method of claim 7 , further comprising:

forming a passivation layer over the second encapsulant, the redistribution structure and the conductive pads, and in contact with the conductive terminals.

11 . A manufacturing method of a package, comprising:

providing a wafer substrate;

bonding a die to the wafer substrate;

encapsulating the die by a first etch stop layer and a first encapsulant;

forming a redistribution structure over the die, the first etch stop layer and the first encapsulant, and electrically connected with the die;

performing a first etching process to partially remove the redistribution structure to form a first opening pattern exposing the first encapsulant;

performing a second etching process using the etched redistribution structure as an etching mask to remove the first encapsulant to form a second opening pattern exposing the first etch stop layer; and

forming a dielectric structure in the first opening pattern and the second opening pattern, and laterally encapsulate the die and the redistribution structure.

12 . The method of claim 11 , wherein the redistribution structure is form to comprise a second etch stop layer in contact with the first etch stop layer and the first encapsulant; and a dielectric layer on the second etch stop layer.

13 . The method of claim 12 , wherein the first etching process for forming the first opening pattern comprises:

a first etching step of partially removing the dielectric layer of the redistribution structure, while remaining the second etch stop layer intact; and

a second etching step of partially removing the second etch stop layer to form the first opening pattern.

14 . The method of claim 11 , wherein the second etching process for forming the second opening pattern comprises: completely removing the first encapsulant without the presence of residue, while remaining the first etch stop layer intact.

15 . The method of claim 11 , wherein a sidewall of the first opening pattern defined by the redistribution structure and an outer side surface of a vertical portion of the first etch stop layer on the die have an offset.

16 . The method of claim 11 , further comprising:

forming conductive pads over the redistribution structure;

forming a passivation layer over the dielectric structure, the redistribution structure and the conductive pads; and

forming conductive terminals over the conductive pads and the passivation layer.

17 . The method of claim 16 , further comprising:

performing a singulation process to cut through the passivation layer, the dielectric structure, the first etch stop layer and the wafer substrate.

18 . A manufacturing method of a package, comprising:

providing a wafer substrate;

bonding a die to the wafer substrate;

forming a etch stop layer and a first encapsulant laterally surrounding the die;

forming a redistribution structure over the etch stop layer and the first encapsulant, and electrically connected with the die;

forming a masking layer on the redistribution structure;

patterning the redistribution structure using the masking layer as a mask to expose the first encapsulant;

removing the first encapsulant to expose the etch stop layer; and

forming a dielectric structure over the exposed etch stop layer and laterally surrounding the die and the redistribution structure.

19 . The method of claim 18 , wherein the masking layer is removed before the dielectric structure is formed.

20 . The method of claim 18 , wherein the dielectric structure is formed to have a top surface substantially coplanar with a top surface of the redistribution structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2022
From: YEH, DER-CHYANG; YEH, SUNG-FENG; HONG, JIAN-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060630/0973 →
Continuity (1)
Related Publication 20240030186A1 · Jan 25, 2024
References Cited (16)
US 7812459B2 · Yu · 2010 [cited by examiner]
US 8993380B2 · Hou et al. · 2015 [cited by applicant]
US 9281254B2 · Yu et al. · 2016 [cited by applicant]
US 9299649B2 · Chiu et al. · 2016 [cited by applicant]
US 9372206B2 · Wu et al. · 2016 [cited by applicant]
US 9425126B2 · Kuo et al. · 2016 [cited by applicant]
US 9443783B2 · Lin et al. · 2016 [cited by applicant]
US 9461018B1 · Tsai et al. · 2016 [cited by applicant]
US 9496189B2 · Yu et al. · 2016 [cited by applicant]
US 9620488B2 · Yu · 2017 [cited by examiner]
US 9666502B2 · Chen et al. · 2017 [cited by applicant]
US 9735131B2 · Su et al. · 2017 [cited by applicant]
US 10937743B2 · Chen · 2021 [cited by examiner]
US 11031354B2 · Chen · 2021 [cited by examiner]
US 11063019B2 · Chen · 2021 [cited by examiner]
US 20220367364A1 · Jeon · 2022 [cited by examiner]