Cut metal gate processes
A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.
1 . A method comprising:
performing a plurality of cycles to form a trench in a feature, wherein the plurality of cycles comprise:
depositing a dielectric layer; and
etching a portion of the feature underlying a bottom portion of the dielectric layer to extend the trench downwardly;
removing the dielectric layer from the trench, wherein the removing the dielectric layer comprises a sublimation process; and
filling the trench with a dielectric material to form a dielectric isolation region.
2 . The method of claim 1 , wherein the dielectric layer and the dielectric material comprise a same dielectric material.
3 . The method of claim 2 , wherein the dielectric layer and the dielectric material comprise silicon oxide.
4 . The method of claim 1 , wherein the removing the dielectric layer comprises:
reacting the dielectric layer with a gas to form a solid layer; and
performing the sublimation process by baking a wafer that comprises the dielectric layer.
5 . The method of claim 4 , wherein the reacting the dielectric layer with the gas comprises reacting silicon oxide with hydrogen fluoride and ammonia.
6 . The method of claim 4 , wherein the baking the wafer is performed at a temperature higher than about 100° C.
7 . The method of claim 1 , wherein the feature that is etched by the plurality of cycles comprises a gate stack, and wherein after the dielectric layer is removed, sidewalls of the gate stack are exposed to the trench.
8 . The method of claim 1 , wherein the dielectric layer is deposited using process gases comprising SiCl 4 and O 2 .
9 . The method of claim 1 , wherein an entirety of the dielectric layer is removed from the trench.
10 . The method of claim 1 , wherein in each of the plurality of cycles, the trench extends down vertically.
11 . A method comprising:
forming a gate stack on a semiconductor fin, wherein the semiconductor fin is over a bulk portion of a semiconductor substrate;
forming a Contact Etch Stop Layer (CESL) on opposing sides of the gate stack;
forming an Inter-Layer Dielectric (ILD) on the CESL;
forming a trench in the gate stack, wherein during the forming the trench, a dielectric layer is formed in the trench, and wherein the trench and the dielectric layer penetrate through the gate stack;
removing the dielectric layer comprising:
converting the dielectric layer into a solid layer; and
baking the solid layer as a gas; and
depositing a dielectric material into the trench.
12 . The method of claim 11 , wherein the forming the trench comprises a plurality of cycles, each comprising:
depositing a portion of the dielectric layer; and
etching a portion of the gate stack and a bottom portion of the dielectric layer at a bottom of the trench to extend the trench downwardly.
13 . The method of claim 11 further comprising, when the gate stack is etched, etching gate spacers that are on sidewalls of the gate stack to extend the trench into the gate spacers, wherein portions of the dielectric layer in the trench and on the gate spacers are also removed.
14 . The method of claim 11 further comprising, when the gate stack is etched, etching portions of the ILD on a side of the gate stack to extend the trench into the ILD, wherein portions of the dielectric layer in the trench and on the ILD are also removed.
15 . The method of claim 11 , wherein the trench further extends into a dielectric isolation region that is underlying the gate stack.
16 . The method of claim 11 , wherein the removing the dielectric layer comprises removing silicon oxide, and the depositing the dielectric material also comprises depositing silicon oxide.
17 . The method of claim 11 , wherein the dielectric layer comprises portions on sidewalls of the bulk portion of the semiconductor substrate.
18 . A method comprising:
forming a conductive region over a shallow trench isolation region;
forming an inter-layer dielectric, wherein the conductive region is in the inter-layer dielectric;
forming a trench in the conductive region, wherein at a time the forming the trench is finished, a dielectric layer is left in the trench, wherein the trench extends into a semiconductor substrate underlying the shallow trench isolation region, and the dielectric layer covers first sidewalls of the conductive region;
reacting the dielectric layer with a gas to form an additional layer;
removing the additional layer through a baking process; and
filling a dielectric isolation region into the trench, wherein second sidewalls of the semiconductor substrate are exposed to the trench when the dielectric layer starts to be reacted with the gas.
19 . The method of claim 18 , wherein the conductive region comprises a gate stack, and wherein the dielectric isolation region electrically insulates two portions of the gate stack from each other.
20 . The method of claim 18 , wherein at a time the dielectric layer starts to be reacted with the gas, a bottommost end of the dielectric layer is higher than a bottom of the trench.