Integrated circuit device
Provided is an integrated circuit device including a substrate including a first active area and a second active area each extending in a first direction, a bit line extending in the first direction in a first trench of the substrate and arranged between the first active area and the second active area in a second direction perpendicular to the first direction, a contact structure including a lower contact contacting the bit line and an upper contact contacting the first active area, a word line extending in the second direction in a second trench of the substrate, a plurality of landing pads on the substrate, and a capacitor structure including a plurality of lower electrodes on the plurality of landing pads, wherein the bit line and the word line are buried under an upper surface of the substrate.
1 . An integrated circuit device comprising:
a substrate including a first active area and a second active area each extending in a first direction;
a bit line extending in the first direction in a first trench of the substrate and arranged between the first active area and the second active area in a second direction perpendicular to the first direction;
a first capping insulation layer on the bit line in the first trench of the substrate;
a first spacer between the substrate and the bit line;
a contact structure including a lower contact and an upper contact on the lower contact, the lower contact being in contact with the bit line and the upper contact being in contact with the first active area;
a word line extending in the second direction in a second trench of the substrate;
a second capping insulation layer on the word line in the second trench of the substrate;
a second spacer between the substrate and the word line;
a plurality of landing pads on the substrate; and
a capacitor structure including a plurality of lower electrodes on the plurality of landing pads, an upper electrode over the plurality of lower electrodes, and a dielectric film between the plurality of lower electrodes and the upper electrode,
the bit line and the word line being buried under an upper surface of the substrate, and
the plurality of landing pads being on the upper surface of the substrate.
2 . The integrated circuit device of claim 1 , wherein
an upper surface of the contact structure is at a vertical level equal to or lower than the upper surface of the substrate.
3 . The integrated circuit device of claim 1 , wherein
a distance between the bit line and the upper surface of the substrate is greater than a distance between the word line and the upper surface of the substrate.
4 . The integrated circuit device of claim 1 , wherein
the first spacer includes a first portion extending along a sidewall of the substrate defining the first trench, and
the lower contact extends along the first portion of the first spacer.
5 . The integrated circuit device of claim 1 , wherein
the first active area has a recessed surface thereon, and
the upper contact protrudes laterally from the lower contact in the second direction and contacts the recessed surface of the first active area.
6 . The integrated circuit device of claim 1 , wherein
a length of the upper contact in the second direction is greater than that of the lower contact in the second direction.
7 . The integrated circuit device of claim 1 , further comprising:
a contact cover insulating layer covering the contact structure.
8 . The integrated circuit device of claim 1 , wherein
the plurality of lower electrodes are arranged in a honeycomb structure.
9 . The integrated circuit device of claim 8 , wherein
the honeycomb structure includes six lower electrodes positioned at six vertexes of a hexagon and a single lower electrode positioned at a center point of the hexagon.
10 . The integrated circuit device of claim 9 , wherein
a first line connecting center points of a pair of most neighboring lower electrodes among the plurality of lower electrodes in the first direction has a first length in the first direction,
a second line connecting center points of a pair of most neighboring lower electrodes in a direction crossing the first direction and the second direction among the plurality of lower electrodes has a second length in the second direction, and
the first length is greater than the second length.
11 . The integrated circuit device of claim 8 , further comprising:
a support configured to connect the plurality of lower electrodes to each other to support the plurality of lower electrodes, and including a plurality of opening areas.
12 . The integrated circuit device of claim 1 , further comprising:
two device isolation layers in the substrate, the two device isolation layers spaced apart in the first direction with the first active area therebetween.
13 . The integrated circuit device of claim 1 , wherein
the first active area includes source/drain regions divided in the first direction, and
some of the source/drain regions are in contact with the contact structure, and a rest of the source/drain regions are in contact with the plurality of landing pads.
14 . An integrated circuit device comprising:
a substrate including an active area extending in a first direction;
at least one pair of device isolation layers in the substrate, the at least one pair of device isolation spaced apart in the first direction with the active area therebetween;
a bit line buried in the substrate and extending in the first direction;
a plurality of word lines buried in the substrate and extending in a second direction perpendicular to the first direction;
a contact structure including a lower contact connected to the bit line and an upper contact connected to an upper portion of the active area;
a plurality of landing pads on the substrate; and
a capacitor structure including a plurality of lower electrodes positioned on the plurality of landing pads, respectively,
the active area including source/drain regions divided by the plurality of word lines in the first direction, and
some of the source/drain regions being in contact with the upper contact, and a rest of the source/drain regions being in contact with the plurality of landing pads.
15 . The integrated circuit device of claim 14 , wherein
the bit line and the plurality of word lines are under an upper surface of the substrate,
the plurality of landing pads is on the upper surface of the substrate, and
an upper surface of the contact structure is at a level equal to or lower than the upper surface of the substrate.
16 . The integrated circuit device of claim 15 , further comprising:
a first capping insulation layer on the bit line; and
a first spacer positioned between the bit line and the substrate and between the lower contact and the substrate,
wherein
the lower contact extends along the first spacer, and
the upper contact extends laterally beyond the first spacer.
17 . The integrated circuit device of claim 16 , wherein
the first spacer includes silicon nitride, and
the first capping insulation layer includes silicon oxide.
18 . The integrated circuit device of claim 14 , wherein
the plurality of lower electrodes are arranged in a honeycomb structure, and
the honeycomb structure includes six lower electrodes positioned at six vertexes of a hexagon and a single lower electrode positioned at a center point of the hexagon.
19 . The integrated circuit device of claim 18 , wherein
among the plurality of the lower electrodes, a pair of most neighboring lower electrodes are arranged in a line in the first direction.
20 . An integrated circuit device comprising:
a substrate including a first active area and a second active area each extending in a first direction;
a bit line extending in the first direction in a first trench of the substrate and arranged between the first active area and the second active area in a second direction perpendicular to the first direction;
a first capping insulation layer on the bit line;
a contact structure including a lower contact and an upper contact on the lower contact, the lower contact being in contact with the bit line and the upper contact being in contact with the first active area;
a first spacer positioned between the substrate and the bit line and between the substrate and the lower contact, the first spacer contacting the lower contact;
two device isolation layers in the substrate, the two device isolation layers spaced apart in the first direction with the first active area therebetween;
a plurality of word lines extending in the second direction and arranged in a plurality of second trenches provided in the substrate, the plurality of second trenches passing through the first active area in the second direction;
a plurality of second capping insulation layers positioned on the plurality of word lines, respectively;
a plurality of second spacers arranged between the substrate and the plurality of word lines, respectively;
a plurality of landing pads on the substrate; and
a capacitor structure including a plurality of lower electrodes on the plurality of landing pads, respectively, an upper electrode over the plurality of lower electrodes, and a dielectric film between the plurality of lower electrodes and the upper electrode,
the bit line, the contact structure, and the plurality of word lines being buried under an upper surface of the substrate,
the plurality of landing pads being on the upper surface of the substrate, and
a pair of most neighboring lower electrodes among the plurality of the lower electrodes being arranged in a line in the first direction.