Microprocessor with apparatus and method for handling of instructions with long throughput
A processor includes a time counter and a time-resource matrix and statically dispatches instructions if the resources are available based on data stored in the time-resource matrix. Execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline. The execution of a second instruction to a functional unit may be replayed due to the throughput time of a first instruction to the same functional unit. A busy bit and next available time of the functional unit are set when the first instruction is sent to the functional unit are the indication to replay the second instruction.
1 . A processor comprising:
a time counter storing a time count representing a current time of the processor, wherein the time count is incremented periodically;
an instruction issue unit coupled to the time counter that receives a first instruction, and issues the first instruction with a first preset execution time based on the time count;
an execution queue coupled to the time counter and the instruction issue unit that receives the first instruction from the instruction issue unit, and dispatches the first instruction to a functional unit when the first preset execution time corresponds to the time count; and
dispatch circuitry that determines if the functional unit is busy at the first preset execution time and if so then retains the first instruction in the execution queue and causes replay of the first instruction based on a next free time provided by a next free time register coupled to the dispatch circuitry.
2 . The processor of claim 1 further comprising:
a clock circuit that causes the time counter to increment the time count with each clock cycle of the clock circuit; and
wherein the time counter comprises an N-bit counter which counts from a zero count to an Nth-bit count value, which represents a largest preset time for the instruction issue unit to issue an instruction;
wherein the N-bit counter returns to the zero count after reaching the Nth-bit count value.
3 . The processor of claim 1 further comprising:
a register scoreboard storing a write time of a selected register from a plurality of registers in a register file, wherein the write time is a preset time based on the time count;
an instruction decode unit coupled to the register scoreboard, wherein the instruction decode unit reads a write time for each source operand of the first instruction from the register scoreboard, and wherein the register scoreboard uses one or more write times to determine an execution time for the first instruction; and
a time-resource matrix unit, coupled to the register scoreboard, comprising a plurality of time-resource registers for storing information relating to available resources for each time count of an N-bit time counter;
wherein the time-resource registers store information for resources that include at least one of: a plurality of read buses, a plurality of write buses, and a plurality of each type of functional units; and
wherein the time-resource matrix unit uses the execution time of the first instruction to further check availability of the plurality of read buses, the plurality of write buses, and the plurality of each type of functional units to issue the first instruction at a second preset execution time.
4 . The processor of claim 3 , wherein the plurality of time-resource registers include a shared resource wherein the shared resource can be read and incremented by one or more of the instruction issue unit, a coprocessor, or by replay of an instruction.
5 . The processor of claim 1 further comprising:
read control circuitry having registers storing time count entries specifying when operands may be read and transported on a read bus, and wherein the read control circuitry further accesses a register scoreboard to determine availability of a first register in a register file, wherein if a write time of the first register is the same as the time count then data is forwarded from the first register instead of being read from the register file.
6 . The processor of claim 5 further comprising:
a write control circuitry having a plurality of write bus control registers, each write bus control register storing a time count entry specifying when result data may be transported on a write bus and written to a second register of the register file;
wherein the write control circuitry further accesses the register scoreboard to clear a valid bit if the write time stored in the write bus control register is the same as the time count.
7 . The processor of claim 6 wherein the execution queue stores a plurality of instructions, the functional unit is one of a plurality of functional units and each instruction includes a first read time which is represented by a preset time count wherein the execution queue dispatches instructions to at least a selected functional unit and wherein dispatching of a long throughput instruction to the selected functional unit sets a busy bit associated with the selected functional unit and records a next available time of the functional unit.
8 . The processor of claim 7 wherein the read control circuitry is synchronized with a second read time in the execution queue.
9 . The processor of claim 7 wherein each instruction of the execution queue includes a replay bit to replay a corresponding instruction if such corresponding instruction was not completed at a corresponding preset time.
10 . The processor of claim 9 wherein each instruction in the execution queue further includes an immediate data field and a source valid bit that is set at a time at which the replay bit is set, and a valid source operand data is written into the immediate data field.
11 . A processor comprising:
a clock circuit;
a time counter storing a time count representing a specific time of operation of the processor, wherein the time count is incremented by the clock circuit;
a time-resource matrix coupled to a register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter;
an instruction issue unit coupled to the time counter for receiving a first instruction, and issuing or stalling the first instruction at a first preset execution time, as represented by the time count, based on availability of the available resources as provided by the time-resource matrix;
an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to a functional unit when the first preset execution time matches the time count;
dispatch circuitry to determine if a busy bit of the functional unit is set to replay the first instruction at a new read time determined from a time count at which the functional unit is next available;
the register scoreboard storing a write time of a register in a register file, wherein the write time is a future time specified by the time count;
an instruction decode unit coupled to the register scoreboard, the instruction decode unit reading a write time for each source operand of a selected instruction from the register scoreboard, and using the write times corresponding to the selected instruction to determine an execution time for the selected instruction; and
wherein the available resources include at least one of a plurality of read buses, a plurality of write buses, and a plurality of functional units.
12 . A computer program product for issuing an instruction, the computer program product stored on a non-transitory computer readable storage medium and including instructions for causing a computer system to execute a method that is executable by a processor, the method comprising:
issuing an instruction to an execution queue to execute at a preset time, wherein the preset time is a time defined by a time count from a periodically incremented time counter;
dispatching the instruction from the execution queue to a functional unit when the preset time corresponds to the time count; and
retaining the instruction in the execution queue and replaying the instruction at a next free time if a dispatch circuitry determines that the functional unit is busy at the preset time.
13 . The computer program product of claim 12 wherein the method further comprises:
operating the time counter to provide a maximum time count corresponding to a latest preset time to issue an instruction.
14 . The computer program product of claim 13 wherein the method further comprises:
storing a write time of a register of a register file wherein the write time is a preset time defined by the time count.
15 . The computer program product of claim 14 wherein the method further comprises:
storing information corresponding to available resources for each time count in a time-resource matrix, wherein the resources comprise at least one of a plurality of read buses, a plurality of write buses, and a plurality of functional units.
16 . The computer program product of claim 15 wherein the method further comprises:
storing in a register of a read control circuitry a read time that specifies when data may be read from a register file and transported on a read bus.
17 . The computer program product of claim 16 wherein the method further comprises:
storing in a register of a write control circuitry a write time that specifies when result data may be transported on a write bus and written to a register of the register file.
18 . The computer program product of claim 17 wherein the method further comprises:
storing a plurality of instructions in the execution queue, wherein each instruction includes a read time defined by the time count.
19 . The computer program product of claim 18 wherein the method further comprises:
synchronizing the read time of the execution queue with the read control circuitry.