Microprocessor with apparatus and method for replaying load instructions
A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching load/store instructions if the required resources are available based on data stored in the time-resource matrix, and wherein execution times for the load/store instructions use a time count from the time counter to specify when the load/store instructions may be provided to a load-store unit pipeline. The execution times of the load instruction is based on the data cache hit latency time. A delay of the load/store instruction causes the load/store instruction to be replayed with known or estimated time. A load-store unit employs multiple bank queues to access multiple data banks of a data cache.
1 . A processor comprising:
a time counter storing a time count representing a current time of the processor, wherein the time count is incremented periodically;
an instruction issue unit coupled to the time counter that receives a first load/store instruction, and issues the first load/store instruction with a first preset execution time based on the time count;
an execution queue, coupled to the time counter and the instruction issue unit, that receives the first load/store instruction from the instruction issue unit, and dispatches the first load/store instruction to a functional unit when the first preset execution time corresponds to the time count;
dispatch logic that determines if the load/store instruction will be replayed with known or estimated delay cycles for replay;
a register scoreboard storing a write time of a selected register from a plurality of registers in a register file, wherein the write time is a future time based on the time count;
an instruction decode unit coupled to the register scoreboard, wherein the instruction decode unit reads a write time for each source operand of a second instruction from the register scoreboard, and uses the one or more write times to determine an execution time for the second instruction; and
a time-resource matrix unit comprising a plurality of the time-resource registers for storing information relating to available resources for each time count of the N-bit time counter, the time-resource registers storing information for resources that include at least one of: a plurality of read buses, a plurality of write buses, and a plurality of each type of functional units, the time-resource matrix unit checking availability of resources comprising read buses, the write buses, and the functional units, for replaying a first instruction at a second preset execution time, and designating resources necessary to replay the first instruction at the second preset execution time as busy.
2 . The processor of claim 1 further comprising:
a clock circuit that causes the time counter to increment the time count with each clock cycle of the clock circuit; and
wherein the time counter comprises an N-bit counter which counts from a zero count to an Nth-bit count value, which represents a largest future time for the instruction issue unit to issue a first instruction; and
wherein the N-bit counter returns to a zero count after reaching the Nth-bit value.
3 . The processor of claim 1 further comprising:
a read control unit having registers storing time count entries specifying when operands may be read and transported on a read bus, and wherein the read control unit further accesses a register scoreboard to determine availability of a first register in a register file, wherein if a write time of the first register is the same as the time count then data is forwarded from the first register instead of being read from the register file.
4 . The processor of claim 3 further comprising:
a write control unit having a plurality of write bus control registers, each write bus control register storing a time count entry specifying when result data may be transported on a write bus and written to a second register of the register file;
wherein the write control unit further accesses the register scoreboard to clear a valid bit if the write time stored in the write bus control register is the same as the time count.
5 . The processor of claim 4 wherein the execution queue stores a plurality of instructions, and each instruction includes a first read time which is represented by a future time count wherein the execution queue dispatches instructions to at least one functional unit and wherein the read control unit is synchronized with the first read time in the execution queue.
6 . The processor of claim 5 wherein the execution queue includes a replay bit corresponding to each instruction in the execution queue, the execution queue operating to:
respond to setting of the replay bit for a particular instruction by updating a read time for the particular instruction with a new read time corresponding to a future time count;
dispatch the particular instruction to at least one functional unit to cause replay of the particular instruction by causing access of the time-resource matrix to determine availability of resources; and
set an unknown bit corresponding to the particular instruction if at least one resource to execute the particular instruction is not available at the new read time.
7 . The processor of claim 6 wherein the execution queue stores one or more load/store instructions and dispatches each load/store instruction to a load-store unit, wherein each load/store instruction requires multiple clock cycles to complete in the load-store unit and a load/store instruction remains designated as valid in the execution queue until the load/store instruction completes or replays in the load-store unit, wherein a time to replay the load/store instruction is known or estimated.
8 . The processor of claim 7 wherein, the dispatch logic:
determines that load data for a load instruction will be delayed and sets a replay bit for the load instruction in the execution queue;
updates a read time corresponding to the load instruction based on an estimated latency time and the time count; and
sets an unknown bit corresponding to the load instruction if data to be loaded by the load instruction is not received within the estimated latency time.
9 . The processor of claim 8 wherein the dispatch logic sets an unknown bit corresponding to a first instruction of the execution queue to cause the first instruction to be replayed in accordance with a retire order of the first instruction.
10 . The processor of claim 9 wherein the instruction repeatedly accesses the time-resource matrix for available resources until resources are available to permit dispatch of the instruction to a functional unit in a next cycle.
11 . The processor of claim 7 further comprising a load/store unit that comprises a data bank queue for a data bank of the data cache wherein a valid entry in the data bank queue has higher priority to access the data bank of the data cache than a first load/store instruction to the same data bank wherein a number of valid entries of the data bank queue is used to determine a new write time for replay of the first load/store instruction.
12 . The processor of claim 10 wherein the data bank queue comprises a multiplex to select a valid entry in the data bank queue or an address corresponding to the first load/store instruction.
13 . A processor comprising:
a clock circuit;
a time counter storing a time count representing a specific time of operation of the processor, wherein the time count is incremented by the clock circuit;
a time-resource matrix coupled to a register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter and wherein the time-resource matrix comprises busy signals of the resources based on the time count;
an instruction issue unit coupled to the time counter for receiving a first load/store instruction, and issuing or stalling the first load/store instruction at a preset execution time as represented by the time count, based on availability of the available resources as provided by the time-resource matrix;
an execution queue coupled to the time counter and the instruction issue unit to receive the first load/store instruction from the instruction issue unit, and dispatch the first load/store instruction to a functional unit when the preset execution time matches the time count;
dispatch logic to track the first load/store instruction through a load-store unit pipeline and replay the first load/store instruction if the first load/store instruction cannot be completed by an expected cycle wherein the execution queue replays the load instruction by determining availability of write buses using the busy signals;
the register scoreboard storing a write time of a register in a register file, wherein the write time is a future time specified by the time count;
an instruction decode unit coupled to the register scoreboard, the instruction decode unit reading a write time for each source operand of a selected instruction from the register scoreboard, and using the write times corresponding to the selected instruction to determine an execution time for the selected instruction; and
wherein the available resources include at least one of a plurality of read buses, a plurality of write buses, and a plurality of functional units.
14 . The processor of claim 13 further comprising a load/store unit that comprises a data bank queue for a data bank of a data cache wherein a valid entry in the data bank queue has higher priority to access the data bank of the data cache than a first load/store instruction to the same data bank wherein a number of valid entries of the data bank queue is used to determine a new write time for replay of the first load/store instruction.
15 . A computer program product for issuing an instruction, the computer program product stored on a non-transitory computer readable storage medium and including instructions for causing a computer system to execute a method that is executable by a processor, the method comprising:
issuing a load/store instruction to an execution queue or stalling execution of the load/store instruction in an instruction issue unit;
executing the load/store instruction at a future time depending on availability of resources specified in a time-resource matrix, wherein the future time is a time defined by a time count from a periodically incremented time counter;
replaying the load/store instruction if the load/store instruction cannot be completed at the future time;
operating the time counter to provide a maximum time count corresponding to a latest future time to issue an instruction;
storing a write time of a register of a register file wherein the write time is a future time defined by the time count; and
storing information corresponding to available resources for each time count in the time-resource matrix, wherein the resources comprise at least one of a plurality of read buses, a plurality of write buses, and a plurality of functional units;
wherein the time-resource matrix further comprise a busy signal for each resource based on the time count.
16 . The computer program product of claim 15 wherein the method further comprises:
storing in a register of a read control unit a read time that specifies when data may be read from a first register of a register file and transported on a read bus; and
storing in a register of a write control unit a write time that specifies when result data may be transported on a write bus and written to a second register of the register file.
17 . The computer program product of claim 16 wherein the method further comprises:
storing a plurality of instructions in an execution queue, wherein each instruction includes a read time defined by the time count; and
synchronizing the read time of each instruction in the execution queue with the read control unit.
18 . The computer program product of claim 17 , wherein the method further comprises:
operating the execution queue to dispatch load/store instructions to a load-store unit;
tracking each load/store instruction through the load-store unit; and
replaying any load/store instruction if such load/store instruction is not completed in the load-store unit at an expected time wherein a time to replay such load/store instruction is known or estimated for different types of delays.
19 . The computer program product of claim 18 , wherein the method further comprises:
providing for the load-store unit a data bank queue corresponding to a data bank of a data cache wherein a valid entry in the data bank queue has higher priority to access the data bank of the data cache than a first load/store instruction to the same data bank wherein a number of valid entries of the data bank queue is used to determine a new write time for replay of the first load/store instruction.
20 . The computer program product of claim 19 wherein the method further comprises:
replaying a load instruction to write load data back to the register file by determining if a write bus is available based on the busy signal of the time-resource matrix corresponding to the load instruction.