Heterogeneous integration structure with voltage regulation
Heterogeneous integration semiconductor packages with voltage regulation are described. A semiconductor device can include a chip including a memory device and a plurality of through-silicon-vias (TSVs). The semiconductor device can further include a processor arranged on top of the chip. The processor can be configured to communicate with the memory device via a plurality of interconnects. The semiconductor device can further include at least one voltage regulator arranged on top of the chip. The at least one voltage regulator can be configured to regulate power being provided from the plurality of TSVs to the processor.
1 . A semiconductor device comprising:
a chip including a memory device and a plurality of through-silicon-vias (TSVs);
a processor arranged on top of the chip, wherein the processor is configured to communicate with the memory device via a plurality of interconnects;
at least one voltage regulator arranged on top of the chip, the at least one voltage regulator being configured to regulate power being provided from the plurality of TSVs to the processor; and
at least one optical chip configured to transfer regulated voltage from the at least one voltage regulator to the processor.
2 . The semiconductor device of claim 1 , wherein the at least one voltage regulator includes:
a first voltage regulator configured to regulate power being provide from the plurality of TSVs to the processor; and
a second voltage regulator configured to regulate power being provide from the plurality of TSVs to the memory device.
3 . The semiconductor device of claim 1 , wherein the at least one voltage regulator is configured to output regulated power to the processor via back-end-of-line (BEOL) wires.
4 . The semiconductor device of claim 1 , wherein:
the chip is arranged on top of a substrate;
the semiconductor device further includes another memory device arranged on top of the substrate; and
a memory controller is embedded in the chip, the memory controller being configured to perform memory operations between the memory device and said another memory device.
5 . The semiconductor device of claim 1 , wherein the chip and the processor are connected in a face-to-face (F2F) configuration.
6 . The semiconductor device of claim 1 , wherein the plurality of TSVs are arranged on a periphery of the chip.
7 . The semiconductor device of claim 1 , wherein the memory device in the chip is a three-dimensional (3D) stacked memory device.
8 . A semiconductor device comprising:
a chip arranged on top of a substrate, the chip including a memory device and a plurality of through-silicon-vias (TSVs), the memory device being configured to store data associated with an artificial intelligence application;
an accelerator arranged on top of the chip, wherein the accelerator is configured to communicate with the memory device via a plurality of interconnects, and the accelerator is configured to use data stored in the memory device to perform a specific task for the artificial intelligence application;
at least one voltage regulator arranged on top of the chip, the at least one voltage regulator being configured to regulate power being provided from the plurality of TSVs to the accelerator; and
at least one optical chip configured to transfer regulated voltage from the at least one voltage regulator to the accelerator.
9 . The semiconductor device of claim 8 , wherein the at least one voltage regulator includes:
a first voltage regulator configured to regulate power being provide from the plurality of TSVs to the accelerator; and
a second voltage regulator configured to regulate power being provide from the plurality of TSVs to the memory device.
10 . The semiconductor device of claim 8 , wherein the at least one voltage regulator is configured to output regulated power to the accelerator via back-end-of-line (BEOL) wires.
11 . The semiconductor device of claim 8 , further comprising another memory device arranged on top of the substrate, wherein a memory controller is embedded in the chip, and the memory controller is configured to perform memory operations between the memory device and said another memory device.
12 . The semiconductor device of claim 8 , wherein the chip and the accelerator are connected in a face-to-face (F2F) configuration.
13 . The semiconductor device of claim 8 , wherein the plurality of TSVs are arranged on a periphery of the chip.
14 . The semiconductor device of claim 8 , wherein the memory device in the chip is a three-dimensional (3D) stacked memory device.
15 . A method comprising:
forming a plurality of TSVs on a frame of a memory power chip, wherein the memory power chip includes the frame and a memory device;
attaching the memory power chip with the plurality of TSVs on top of a substrate;
attaching a processor and at least one voltage regulator to a top surface of the memory power chip; and
attaching at least one optical chip to the top surface of the memory power chip.
16 . The method of claim 15 , wherein the processor is an accelerator configured to perform a specific task of an artificial intelligence application using data stored in the memory device.
17 . The method of claim 15 , wherein attaching the processor to the top surface of the memory power chip comprises attaching a face of the processor to a face of the memory device of the memory power chip.