Area efficient LV NMOS TWL charge pump
The application generally discloses systems and methods of generating a voltage waveform having an amplitude three times an input voltage amplitude using a plurality of low voltage (LV) triple well (TWL) N-type field effect devices. The method includes: receiving a first input voltage at a first input of a double switch charge transfer switch (CTS) circuit; applying a 2× kick voltage to a first capacitor coupled to a first portion of the double switch CTS circuit, the first capacitor configured to discharge a kick voltage to a source of a first LV TWL N-type field effect device; and applying a 1× kick voltage to a second capacitor coupled a second portion of the double switch CTS circuit, the second capacitor configured to discharge a kick voltage to a source of a second LV TWL N-type field effect device.
1 . A method of generating a voltage waveform having an amplitude three times an input voltage amplitude using a plurality of low voltage (LV) triple well (TWL) N-type field effect devices, the method comprising:
receiving a first input voltage at a first input of a double switch charge transfer switch (CTS) circuit, the double switch CTS circuit comprising a first portion having a first output and a second portion comprising a second output;
applying a 2× kick voltage to a first capacitor coupled to the first portion of the double switch CTS circuit, the first capacitor configured to discharge a kick voltage to a source of a first LV TWL N-type field effect device of the plurality of LV TWL N-type field effect devices; and
applying a 1× kick voltage to a second capacitor coupled to the second portion of the double switch CTS circuit, the second capacitor configured to discharge a kick voltage to a source of a second LV TWL N-type field effect device of the plurality of LV TWL N-type field effect devices.
2 . The method of claim 1 , wherein the output of the first portion is coupled to the output of the second portion to provide a single double switch CTS circuit output.
3 . The method of claim 1 , wherein the double switch CTS circuit includes a plurality of TWL NMOS devices, the plurality of TWL NMOS devices configured to generate the 2× kick voltage.
4 . The method of claim 1 , wherein the first portion of the double switch CTS circuit includes a first control device and the second portion of the double switch CTS circuit includes a second control device, the first and second control device configured to control a gate voltage applied to the first LV TWL N-type field effect device and the gate voltage applied to the second LV TWL N-type field effect device respectively.
5 . The method of claim 4 , wherein the double switch CTS circuit includes a plurality of clock signals configured to furnish a plurality of input clock signals to the CTS circuit, the plurality of clock signals including a first clock signal having a first phase and a second a second clock signal having a second phase.
6 . The method of claim 5 , wherein the plurality of clock signals further include a third clock signal having a third phase and a fourth clock signal having a fourth phase.
7 . The method of claim 6 , wherein the first clock signal and the second clock signal are in a same phase.
8 . The method of claim 7 , wherein the third clock signal and the fourth clock signal are in the same phase.
9 . The method of claim 7 , wherein the first clock signal is furnished to a capacitor coupled to a gate of the first LV TWL N-type field effect device and the second clock signal is furnished to a capacitor coupled to the gate of the second LV TWL N-type field effect device.
10 . The method of claim 9 , wherein the third clock signal is furnished to a capacitor coupled to the source of the first LV TWL N-type field effect device and the third clock signal is furnished to a capacitor coupled to a drain of the second LV TWL N-type field effect device.
11 . The method of claim 10 , wherein the fourth clock signal is furnished to a capacitor coupled to a drain of the first LV TWL N-type field effect device and the fourth clock signal is furnished to a source of the second control device.
12 . A charge pump system comprising:
a plurality of circuit stages configured to increase a voltage applied at an input of each stage, each stage comprising:
a double switch charge transfer switch comprising a plurality of low voltage N-type devices, the double switch charge transfer switch comprising:
a first set of circuitry configured to generate a voltage waveform having an amplitude three times an input voltage amplitude, the first set of circuitry configured to: (i) provide a 2× kick voltage across each terminal of a first low voltage N-type device, and (ii) provide a 1× kick voltage across each terminal of a second low voltage N-type device.
13 . The charge pump system of claim 12 , further comprising a second set of circuitry configured to generate a voltage waveform having an amplitude two times the input voltage amplitude.
14 . The charge pump system of claim 12 , wherein the first set of circuitry includes a first set of low voltage triple well N-type field effect transistors.
15 . The charge pump system of claim 12 , wherein the second set of circuitry includes a second set of low voltage triple well N-type field effect transistors.
16 . The charge pump system of claim 12 , further comprising a HV capacitor coupled to the first set of circuitry, the HV capacitor configured to store a kick voltage applied to the circuit.
17 . The charge pump system of claim 16 , wherein the kick voltage is at least 2×.
18 . A charge pump comprising:
a first set of circuitry configured to generate a voltage waveform having an amplitude three times an input voltage amplitude, the first set of circuitry configured to: (i) provide a 2× kick voltage across each terminal of a first low voltage N-type device, and (ii) provide a 1× kick voltage across each terminal of a second low voltage N-type device.
19 . The charge pump of claim 18 further comprising a double switch charge transfer switch (CTS) circuit comprising a plurality of N-type devices configured to:
apply the 2× kick voltage to a first capacitor coupled to a first portion of the double switch CTS circuit, the first capacitor configured to discharge a kick voltage to a source of a first LV TWL N-type field effect device of a plurality of LV TWL N-type field effect devices; and
apply the 1× kick voltage to a second capacitor coupled a second portion of the double switch CTS circuit, the second capacitor configured to discharge a kick voltage to a source of a second LV TWL N-type field effect device of the plurality of LV TWL N-type field effect devices.
20 . The charge pump of claim 19 , wherein the plurality of N-type devices include a plurality of TWL NMOS devices configured to generate the 2× kick voltage.