Manufacturing method of semiconductor structure
A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.
1 . A manufacturing method of a semiconductor structure, comprising:
providing a first wafer, wherein the first wafer comprises a first substrate and a first device layer, and the first device layer is located on the first substrate;
providing a second wafer, wherein the second wafer comprises a second substrate and a second device layer, and the second device layer is located on the second substrate;
bonding the second device layer to the first device layer;
performing an edge trimming process on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface, wherein the second upper surface is higher than the first upper surface;
forming a first photoresist layer, wherein the first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region;
removing the damaged region by using the first photoresist layer as a mask; and
removing the first photoresist layer.
2 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the first substrate comprises a two-step structure after the edge trimming process is performed.
3 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the edge trimming process comprises:
using a grinder to grind the second wafer and the first wafer to expose the first upper surface; and
moving the grinder and using the grinder to grind the second wafer to expose the second upper surface.
4 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the method of removing the damaged region comprises performing an etching process on the damaged region.
5 . The manufacturing method of the semiconductor structure according to claim 4 , wherein during the etching process, a removal rate of the damaged region of the first substrate is greater than a removal rate of a remaining portion of the first substrate.
6 . The manufacturing method of the semiconductor structure according to claim 4 , wherein the etching process comprises a wet etching process, a dry etching process, or a combination thereof.
7 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the method of forming the first photoresist layer comprises:
forming a photoresist material layer on the first wafer and the second wafer; and
performing an edge bead removal process on the photoresist material layer.
8 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the method of bonding the second device layer to the first device layer comprises a hybrid bonding method.
9 . The manufacturing method of the semiconductor structure according to claim 1 , wherein the method of bonding the second device layer to the first device layer comprises a fusion bonding method.
10 . The manufacturing method of the semiconductor structure according to claim 1 , further comprising:
performing a thinning process on the second substrate.
11 . The manufacturing method of the semiconductor structure according to claim 1 , further comprising:
forming a second photoresist layer on a portion of a sidewall of the first wafer and a sidewall of the second wafer after the first photoresist layer is removed, wherein the second photoresist layer exposes a top surface of the second substrate;
removing the second substrate by using the second photoresist layer as a mask; and
removing the second photoresist layer; and
forming a dielectric layer on a sidewall of the first device layer and a sidewall of the second device layer.
12 . The manufacturing method of the semiconductor structure according to claim 11 , further comprising
exposing a third upper surface of the first substrate after the damaged region is removed, and
further forming the dielectric layer on the third upper surface and a top surface of the second device layer.
13 . The manufacturing method of the semiconductor structure according to claim 11 , wherein the dielectric layer comprises a single-layer structure.
14 . The manufacturing method of the semiconductor structure according to claim 11 , wherein the dielectric layer comprises a multi-layer structure.
15 . The manufacturing method of the semiconductor structure according to claim 11 , wherein the method of removing the second substrate comprises performing a wet etching process on the second substrate.
16 . The manufacturing method of the semiconductor structure according to claim 15 , wherein an etchant used in the wet etching process comprises tetramethylammonium hydroxide.
17 . The manufacturing method of the semiconductor structure according to claim 15 , wherein the second wafer further comprises:
a stop layer, located between the second substrate and the second device layer.
18 . The manufacturing method of the semiconductor structure according to claim 17 , wherein the second substrate is removed by using the stop layer as an etch stop layer.
19 . The manufacturing method of the semiconductor structure according to claim 17 , wherein during the wet etching process, a removal rate of the second substrate is greater than a removal rate of the stop layer.
20 . The manufacturing method of the semiconductor structure according to claim 17 , wherein the stop layer is located between the dielectric layer and the second device layer.