IP Library Granted Patent US 12,599,009
Granted Patent B2
US 12,599,009 · App. 17/327,759 · Granted Apr 7, 2026

Package structure

Inventors: Chun-Wen Lin (Changhua County, TW); Chung-Hao Tsai (Changhua County, TW); Chen-Hua Yu (Hsinchu City, TW); Chuei-Tang Wang (Taichung City, TW); Che-Wei Hsu (Kaohsiung City, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/5389H01L21/4853H01L21/4857H01L21/486H01L21/565H01L23/3114H01L23/5383H01L23/5384H01L23/5386H01L23/66H01L24/19H01L24/20H01Q1/2283H01L2223/6677H01L2224/13101H01L2224/18H01L2224/214H01L2224/81801H01L2924/00014H01L2924/19106
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,599,009
App. No.
17/327,759
Granted
Apr 7, 2026
Kind
B2
Abstract

A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Claims (51)

1 . A package structure, comprising:

an integrated circuit component comprising at least one conductive via;

a first insulating encapsulation, encapsulating the integrated circuit component, and the first insulating encapsulation is free from the at least one conductive via;

a first redistribution structure, located on a first side of the first insulating encapsulation and the integrated circuit component; and

a dielectric layer, located on a second side of the first insulating encapsulation, wherein the first side is opposite to the second side along a stacking direction of the first redistribution structure and the integrated circuit component.

2 . The package structure of claim 1 , further comprising:

a second redistribution structure, located over the dielectric layer, wherein the first insulating encapsulation is between the first redistribution structure and the second redistribution structure; and

vertical connection structures, next to the integrated circuit component and penetrating through the first insulating encapsulation, wherein the vertical connection structures electrically connect the second redistribution structure to the first redistribution structure,

wherein the at least one conductive via is disposed between a semiconductor substrate of a semiconductor die comprised in the integrated circuit component and the first redistribution structure.

3 . The package structure of claim 2 , wherein sidewalls of the vertical connection structures are covered by the first insulating encapsulation.

4 . The package structure of claim 2 , wherein a surface of the second redistribution structure is covered by the first insulating encapsulation.

5 . The package structure of claim 1 , wherein the integrated circuit component is electrically connected to the first redistribution structure through the at least one conductive via, and the at least one conductive via comprises a signal via and a power via, wherein a size of the signal via is less than a size of the power via.

6 . The package structure of claim 5 , wherein the at least one conductive via further comprises a ground via, and a size of the ground via is less than the size of the power via while the size of the ground via is greater than or substantially equal to the size of the signal via.

7 . The package structure of claim 5 , wherein the at least one conductive via further comprises a ground via, and a size of the ground via is substantially equal to the size of the power via while the size of the ground via is greater than the size of the signal via.

8 . A package structure, comprising:

at least one integrated circuit component, comprising:

a semiconductor substrate;

an interconnection structure, disposed on the semiconductor substrate; and

signal terminals and power terminals, located on and electrically connecting to the interconnection structure, wherein a size of each of the signal terminals is less than a size of each of the power terminals;

a first redistribution structure, located on a first side of the at least one integrated circuit component and electrically connected to the at least one integrated circuit component;

an encapsulant, located on a second side of the at least one integrated circuit component, the second side being opposite to the first side; and

an antenna element, located on and electrically coupled to the at least one integrated circuit component, wherein the encapsulant is between the antenna element and the at least one integrated circuit component.

9 . The package structure of claim 8 , wherein each of the signal terminals comprises one signal via, and each of the power terminals comprises one power via.

10 . The package structure of claim 8 ,

wherein each of the signal terminals comprises one signal via and one signal pad, and the signal pad is located between and electrically connecting the signal via and the interconnection structure, and

wherein each of the power terminals comprises one power via and one power pad, and the power pad is located between and electrically connecting the power via and the interconnection structure.

11 . The package structure of claim 8 , wherein the at least one integrated circuit component further comprises:

ground terminals, located on and electrically connecting to the interconnection structure, wherein a size of each of the ground terminals is less than a size of each of the power terminals, and the size of each of the ground terminals is greater than or substantially equal to the size of each of the signal terminals.

12 . The package structure of claim 8 , wherein the at least one integrated circuit component further comprises:

ground terminals, located on and electrically connecting to the interconnection structure, wherein a size of each of the ground terminals is substantially equal to a size of each of the power terminals, and the size of each of the ground terminals is less than the size of each of the signal terminals.

13 . The package structure of claim 8 , wherein the at least one integrated circuit component further comprises:

ground terminals, located on and electrically connecting to the interconnection structure, wherein each of the ground terminals comprises one ground via.

14 . The package structure of claim 8 , wherein the at least one integrated circuit component further comprises:

ground terminals, located on and electrically connecting to the interconnection structure, wherein each of the ground terminals comprises one ground via and one ground pad, and the ground pad is located between and electrically connecting the ground via and the interconnection structure.

15 . The package structure of claim 8 , wherein the antenna element comprises a plurality of patch antennas, and the plurality of patch antennas are arranged into a form of array over the encapsulant.

16 . The package structure of claim 8 , further comprising:

a protection layer over the antenna element and the encapsulant, wherein the antenna element is enclosed by the protection layer and the encapsulant.

17 . A package structure, comprising:

an integrated circuit component, comprising:

a semiconductor substrate; and

signal terminals, ground terminals and power terminals, located on the semiconductor substrate, wherein a size of each of the signal terminals is less than a size of each of the power terminals;

a first redistribution structure, located on a first side of the integrated circuit component and electrically connected to the integrated circuit component;

a second redistribution structure, located on a second side of the integrated circuit component and electrically connected to the integrated circuit component, the second side being opposite to the first side, wherein the integrated circuit component is located between the first redistribution structure and the second redistribution structure;

an encapsulant, located on the second redistribution structure; and

an antenna element, located on and electrically coupled to the integrated circuit component, wherein the encapsulant is between the antenna element and the second redistribution structure, and the second redistribution structure is located between the encapsulant and the integrated circuit component.

18 . The package structure of claim 17 , further comparing:

conductive pillars, next to the integrated circuit component and electrically connecting the first redistribution structure and the second redistribution structure;

an insulating encapsulation, located between the first redistribution structure and the second redistribution structure and covering sidewalls of the integrated circuit component and the conductive pillars; and

conductive terminals, located on and connected to the first redistribution structure, wherein the first redistribution structure is located between the conductive terminals and the integrated circuit component.

19 . The package structure of claim 17 , wherein a size of each of the ground terminals is less than the size of each of the power terminals while the size of each of the ground terminals is greater than or substantially equal to the size of each of the signal terminals.

20 . The package structure of claim 17 , a size of each of the ground terminals is substantially equal to the size of each of the power terminals while the size of each of the ground terminals is greater than the size of each of the signal terminals.

Continuity (4)
Continuation 16944173 · Jul 31, 2020
Continuation 15900808 · Feb 21, 2018
Provisional Application 62590257 · Nov 22, 2017
Related Publication 20210280524A1 · Sep 9, 2021
References Cited (20)
US 9000584B2 · Lin et al. · 2015 [cited by applicant]
US 9048222B2 · Hung et al. · 2015 [cited by applicant]
US 9048233B2 · Wu et al. · 2015 [cited by applicant]
US 9064879B2 · Hung et al. · 2015 [cited by applicant]
US 9111949B2 · Yu et al. · 2015 [cited by applicant]
US 9263511B2 · Yu et al. · 2016 [cited by applicant]
US 9281254B2 · Yu et al. · 2016 [cited by applicant]
US 9368460B2 · Yu et al. · 2016 [cited by applicant]
US 9372206B2 · Wu et al. · 2016 [cited by applicant]
US 9496189B2 · Yu et al. · 2016 [cited by applicant]
US 11488909B2 · Lin · 2022 [cited by examiner]
US 20110254160A1 · Tsai · 2011 [cited by examiner]
US 20130009319A1 · Shao · 2013 [cited by examiner]
US 20130040423A1 · Tung · 2013 [cited by examiner]
US 20150123268A1 · Yu · 2015 [cited by examiner]
US 20150162316A1 · Yu · 2015 [cited by examiner]
US 20150200185A1 · Yu · 2015 [cited by examiner]
US 20170179078A1 · Jung · 2017 [cited by examiner]
US 20190157208A1 · Lin · 2019 [cited by examiner]
US 20210280524A1 · Lin · 2021 [cited by examiner]