IP Library › Granted Patent US 12,604,507
Granted Patent B2
US 12,604,507 · App. 18/185,079 · Granted Apr 14, 2026

Method of manufacturing semiconductor device

Inventors: Futoshi Komatsu (Tokyo, JP); Tomoo Nakayama (Tokyo, JP); Katsuhiro Uchimura (Tokyo, JP); Hiroshi Inagawa (Tokyo, JP)
Assignee: Renesas Electronics Corporation
H10D64/01H01L21/02164H01L21/0217H01L21/02359H01L21/288H01L21/304H01L21/56H10D12/038H10D64/513
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Quick Facts
Patent No.
US 12,604,507
App. No.
18/185,079
Granted
Apr 14, 2026
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.

Claims (33)

1 . A method of manufacturing a semiconductor device, the method comprising:

(a) preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;

(b1) forming a silicon oxide film covering each of the first main surface and the second main surface;

(b2) after the (b1), forming a silicon nitride film covering each of the first main surface and the second main surface;

(b3) forming an element isolation region on the first main surface exposed from the silicon oxide film and the silicon nitride film;

(b4) after the (b3), removing the silicon nitride film on the first main surface while leaving the silicon nitride film on the second main surface, thereby exposing the silicon oxide film on the first main surface;

(c) after the (b4), forming a wiring on the first main surface;

(d) forming a redistribution wiring on the wiring by using a plating method; and

(e) after the (d), grinding the silicon oxide film on the second main surface and grinding the second main surface,

wherein the (e) is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.

2 . The method according to claim 1 , comprising:

(c1) after the (b), removing the silicon nitride film on the second main surface; and

(c2) after the (c1) and before the (c), forming an interlayer insulating film on the first main surface,

wherein, in the (c), the wiring is formed on the interlayer insulating film, and

wherein, in the (d), the redistribution wiring is formed on a part of the wiring.

3 . The method according to claim 1 ,

wherein the (b) includes:

(b5) forming a trench in the first main surface;

(b6) forming the silicon oxide film by oxidation of an inner surface of the trench, the first main surface and the second main surface; and

(b7) forming a gate electrode inside the trench,

wherein the silicon oxide film inside the trench configures a gate insulating film.

4 . A method of manufacturing a semiconductor device, the method comprising:

(a) preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;

(b1) forming a silicon oxide film covering each of the first main surface and the second main surface;

(b2) after the (b1), forming a silicon nitride film covering each of the first main surface and the second main surface;

(b3) forming an element isolation region on the first main surface exposed from the silicon oxide film and the silicon nitride film;

(b4) after the (b3), removing the silicon nitride film on the first main surface while leaving the silicon nitride film on the second main surface, thereby exposing the silicon oxide film on the first main surface;

(c) after the (b4), forming a wiring on the first main surface;

(d) forming a redistribution wiring on the wiring by using a plating method;

(e) after the (d), removing the silicon oxide film on the second main surface, thereby exposing the second main surface;

(f) after the (e), covering the first main surface with a protection tape;

(g) after the (f), grinding the second main surface; and

(h) after the (g), peeling off the protection tape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2023
From: KOMATSU, FUTOSHI; NAKAYAMA, TOMOO; UCHIMURA, KATSUHIRO; INAGAWA, HIROSHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 063014/0130 →
Priority Claims (1)
JP 2022-085268 · May 25, 2022 · national
Continuity (1)
Related Publication 20230387219A1 · Nov 30, 2023
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