Semiconductor package
A semiconductor package includes a package substrate including a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction, semiconductor chips mounted on the first to third chip mounting areas, a first stiffener mounted on the package substrate to separate the first chip mounting area from the second chip mounting area, and a second stiffener mounted on the package substrate to separate the second chip mounting area from the third chip mounting area.
1 . A semiconductor package comprising:
a package substrate comprising a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction;
at least one first semiconductor chip on the first chip mounting area;
at least one second semiconductor chip on the second chip mounting area;
at least one third semiconductor chip on the third chip mounting area;
a first stiffener on the package substrate between the first chip mounting area and the second chip mounting area, the first stiffener comprising a first support pillar on a first corner area of the package substrate, a second support pillar on a second corner area of the package substrate, and a first bridge extending from the first support pillar to the second support pillar in a second direction perpendicular to the first direction and between the first chip mounting area and the second chip mounting area;
a second stiffener on the package substrate between the second chip mounting area and the third chip mounting area, the second stiffener comprising a third support pillar on a third corner area of the package substrate, a fourth support pillar on a fourth corner area of the package substrate, and a second bridge extending from the third support pillar to the fourth support pillar in the second direction and between the second chip mounting area and the third chip mounting area; and
a heat sink spaced apart from the first bridge and the second bridge by a heat dissipation space,
wherein the package substrate has a first edge and a second edge, the first chip mounting area provided between the first edge and the second chip mounting area in a plan view, and the third chip mounting area provided between the second edge and the second chip mounting area in a plan view,
wherein the first stiffener is not provided between the first edge of the package substrate and the at least one first semiconductor chip, in a plan view, and
wherein the second stiffener is not provided between the second edge of the package substrate and the at least one third semiconductor chip, in a plan view.
2 . The semiconductor package of claim 1 , wherein the first bridge and the second bridge continuously contact the package substrate in the second direction.
3 . The semiconductor package of claim 1 , wherein the first bridge and the second bridge are spaced apart from the package substrate.
4 . The semiconductor package of claim 1 , wherein each of the at least one first semiconductor chip and the at least one third semiconductor chip comprises a memory chip,
wherein the at least one second semiconductor chip comprises a system on chip (SOC) and a power management integrated circuit (PMIC) chip,
wherein the first stiffener is not provided on a first side wall of the at least one first semiconductor chip closest to the first edge of the package substrate, and
wherein the second stiffener is not provided on a first side wall of the at least one third semiconductor chip closest to the second edge of the package substrate.
5 . The semiconductor package of claim 4 , wherein the at least one first semiconductor chip is exposed to an outside of the first stiffener in the first direction and a third direction,
wherein the at least one second semiconductor chip is exposed to the outside of the first stiffener and an outside of the second stiffener in the second direction and the third direction,
wherein the at least one third semiconductor chip is exposed to the outside of the second stiffener in the first direction and the third direction, and
wherein the third direction is perpendicular to the first direction and the second direction.
6 . The semiconductor package of claim 1 , wherein the heat sink is on a top surface of the at least one second semiconductor chip through a first thermal interface material (TIM) layer, and
wherein a height of the top surface of the first stiffener and a height of the top surface of the second stiffener are different from a height of the top surface of the at least one second semiconductor chip.
7 . The semiconductor package of claim 1 , further comprising at least one interstiffener bridge extending from the first stiffener to the second stiffener in the first direction,
wherein the at least one interstiffener bridge divides the second chip mounting area into two or more sub-mounting areas, and
wherein the at least one second semiconductor chip comprises a plurality of semiconductor chips on the two or more sub-mounting areas.
8 . The semiconductor package of claim 7 , wherein the at least one interstiffener bridge comprises a first interstiffener bridge and a second interstiffener bridge respectively extending from the first bridge to the second bridge in the first direction and spaced apart from each other in the second direction,
wherein the second chip mounting area comprises a first sub-mounting area adjacent to a first edge of the package substrate, a second sub-mounting area separated from the first sub-mounting area by the first interstiffener bridge, and a third sub-mounting area separated from the second sub-mounting area by the second interstiffener bridge and adjacent to a second edge of the package substrate,
wherein the at least one second semiconductor chip comprises:
a first PMIC chip on the first sub-mounting area;
a system on chip (SOC) on the second sub-mounting area; and
a second PMIC chip on the third sub-mounting area, and
wherein side walls of the SOC are adjacent to the first bridge, the second bridge, the first interstiffener bridge, and the second interstiffener bridge.
9 . The semiconductor package of claim 8 , wherein the first interstiffener bridge and the second interstiffener bridge continuously contact the package substrate in the first direction.
10 . The semiconductor package of claim 8 , wherein the first interstiffener bridge and the second interstiffener bridge are spaced apart from the package substrate.
11 . The semiconductor package of claim 8 , wherein the first bridge, the second bridge, the first interstiffener bridge, and the second interstiffener bridge are included in a single stiffener.
12 . The semiconductor package of claim 11 , wherein the first PMIC chip is exposed to an outside of the single stiffener in the second direction and a third direction,
wherein the SOC is exposed to the outside of the single stiffener in the third direction,
wherein the second PMIC chip is exposed to the outside of the single stiffener in the second direction and the third direction, and
wherein the third direction is perpendicular to the first direction and the second direction.
13 . The semiconductor package of claim 1 , wherein the first stiffener and the second stiffener are symmetrical with each other in a plan view.
14 . The semiconductor package of claim 1 , wherein each of the first corner area, the second corner area, the third corner area, and the fourth corner area comprises a vertex of a surface of the package substrate,
wherein the first chip mounting area is between the first corner area and the second corner area, and
wherein the third chip mounting area is between the third corner area and the fourth corner area.
15 . A semiconductor package comprising:
a package substrate comprising a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction;
a stiffener on the package substrate, the stiffener forming a first heat dissipation space on the first chip mounting area, a second heat dissipation space on the second chip mounting area, and a third heat dissipation space on the third chip mounting area;
at least one first semiconductor chip on the first chip mounting area and in the first heat dissipation space;
at least one second semiconductor chip on the second chip mounting area and in the second heat dissipation space;
at least one third semiconductor chip on the third chip mounting area and in the third heat dissipation space; and
a heat sink,
wherein the stiffener comprises:
a first stiffener comprising a first support pillar on a first corner area of the package substrate, a second support pillar on a second corner area of the package substrate, and a first bridge extending from the first support pillar to the second support pillar in a second direction perpendicular to the first direction and between the first chip mounting area and the second chip mounting area; and
a second stiffener mounted on the package substrate between the second chip mounting area and the third chip mounting area, the second stiffener comprising a third support pillar on a third corner area of the package substrate, a fourth support pillar on a fourth corner area of the package substrate, and a second bridge extending from the third support pillar to the fourth support pillar in the second direction and between the second chip mounting area and the third chip mounting area,
wherein the first heat dissipation space, the second heat dissipation space, and the third heat dissipation space are spaced apart from one another,
wherein the first heat dissipation space, the second heat dissipation space, and the third heat dissipation space are exposed to an outside of the stiffener in a third direction, and
wherein the first bridge and the second bridge are spaced apart from the heat sink by a heat dissipation space.
16 . The semiconductor package of claim 15 , wherein the stiffener comprises:
a first interstiffener bridge extending from the first bridge to the second bridge in the first direction; and
a second interstiffener bridge extending from the first bridge to the second bridge in the first direction and spaced apart from the first interstiffener bridge in the second direction,
wherein the second heat dissipation space comprises:
a first sub-heat dissipation space and a second sub-heat dissipation space separated by the first interstiffener bridge; and
a third sub-heat dissipation space separated from the second sub-heat dissipation space by the second interstiffener bridge, and
wherein the third sub-heat dissipation space is adjacent to the first bridge, the second bridge, the first interstiffener bridge, and the second interstiffener bridge in a plan view.
17 . The semiconductor package of claim 16 , wherein each of the at least one first semiconductor chip and the at least one third semiconductor chip comprises a memory chip, and
wherein the at least one second semiconductor chip comprises:
PMIC chips in the first sub-heat dissipation space and the third sub-heat dissipation space; and
an SOC in the second sub-heat dissipation space.
18 . A semiconductor package comprising:
a package substrate comprising a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction, the second chip mounting area comprising a first sub-mounting area, a second sub-mounting area, and a third sub-mounting area spaced apart from one another in a second direction perpendicular to the first direction;
a first memory chip on the first chip mounting area;
a first PMIC chip on the first sub-mounting area;
a system on chip (SOC) on the second sub-mounting area;
a second PMIC chip on the third sub-mounting area;
a second memory chip on the third chip mounting area;
a first stiffener on the package substrate between the first chip mounting area and the second chip mounting area, the first stiffener comprising a first support pillar on a first corner area of the package substrate, a second support pillar on a second corner area of the package substrate, and a first bridge extending from the first support pillar to the second support pillar in the second direction and between the first chip mounting area and the second chip mounting area;
a second stiffener on the package substrate between the second chip mounting area and the third chip mounting area, the second stiffener comprising a third support pillar on a third corner area of the package substrate, a fourth support pillar on a fourth corner area of the package substrate, and a second bridge extending from the third support pillar to the fourth support pillar in the second direction and between the second chip mounting area and the third chip mounting area;
a first interstiffener bridge extending from the first bridge to the second bridge in the first direction and between the first sub-mounting area and the second sub-mounting area;
a second interstiffener bridge extending from the first bridge to the second bridge in the first direction and between the second sub-mounting area and the third sub-mounting area; and
a heat sink spaced apart from the first bridge and the second bridge by a heat dissipation space, and
wherein side walls of the SOC are adjacent to the first bridge, the second bridge, the first interstiffener bridge, and the second interstiffener bridge,
wherein the package substrate comprises:
a first edge extending in the second direction and closer to the first chip mounting area; and
a second edge extending in the second direction and closer to the third chip mounting area,
wherein the first stiffener is not provided between the first edge of the package substrate and the first memory chip, in a plan view, and
wherein the second stiffener is not provided between the second edge of the package substrate and the second memory chip, in a plan view.
19 . The semiconductor package of claim 18 ,
wherein the first bridge, the second bridge, the first interstiffener bridge, and the second interstiffener bridge are included in a single stiffener,
wherein the first memory chip and the second memory chip are exposed to an outside of the single stiffener in the first direction and a third direction,
wherein the first PMIC chip and the second PMIC chip are exposed to the outside of the single stiffener in the second direction and the third direction,
wherein the SOC is exposed to the outside of the single stiffener in the third direction, and
wherein the third direction is perpendicular to the first direction and the second direction.