Memory device, memory system, and method for data calculation with the memory device
A memory device, a memory system, and a method for data calculation with the memory device are provided. The memory device includes an array of memory cells and a peripheral circuit coupled to the memory cells is provided. The peripheral circuit includes a static random-access memory (SRAM) configured to obtain first data transmitted from a data interface of the memory device, page buffers configured to sense second data from the array of memory cells, and at least one process unit coupled to the SRAM and the page buffers via a data-path bus of the peripheral circuit. At least one process unit is configured to perform calculation based on the first data and the second data. The peripheral circuit further includes a control logic configured to program the second data into the array of memory cells.
1 . A memory device comprising:
an array of memory cells; and
a peripheral circuit coupled to the array of memory cells and comprising:
a static random-access memory (SRAM) configured to obtain first data transmitted from a data interface of the memory device, wherein the first data is programmed into N first data segments, wherein N is a positive integer and N≥2;
page buffers configured to sense second data from the array of memory cells, wherein the second data is programmed into N data groups, each data group comprising M second data segments, wherein M is a positive integer and M≥2;
at least one process unit coupled to the SRAM and the page buffers via a data-path bus of the peripheral circuit, and configured to perform calculation based on the first data and the second data; and
a control logic configured to program the second data into the array of memory cells.
2 . The memory device of claim 1 , wherein
the first data comprises at least one row; and
the control logic is configured to control the SRAM to send each row of the first data to the at least one process unit.
3 . The memory device of claim 2 , wherein
data lengths of the N first data segments are equal; and
an order of the N first data segments remains an original order of the first data segments located in the first data.
4 . The memory device of claim 3 , wherein
the second data comprises M columns; and
the control logic is configured to program each column of the second data into the memory cells.
5 . The memory device of claim 4 , wherein the control logic is configured to program each bit of the second data into one memory cell of the memory cells as a single-level memory cells (SLC).
6 . The memory device of claim 4 , wherein
data lengths of the first data segments and data lengths of the second data segments are equal.
7 . The memory device of claim 6 , wherein each second data segment is assigned with an error checking and correcting (ECC) code.
8 . The memory device of claim 6 , wherein the control logic is configured to control the page buffers to sense the second data from the memory cells into the page buffers based on the second data pattern.
9 . The memory device of claim 6 , wherein each of the at least one process unit comprises M process elements configured to perform convolution operations based on an ith first data segment of the N first data segments and the M second data segments of an ith data group of the N data groups, where i is a positive integer and N≥i≥1.
10 . The memory device of claim 1 , wherein the control logic is configured to:
control the SRAM to send the ith first data segment of the first data to each process element of the M process elements; and
control the page buffers to send the M second data segments to the M process elements.
11 . The memory device of claim 10 , wherein each of the at least one process unit comprises a control element configured to assign the M second data segments to the M process elements one-by-one based on an order of the M second data segments originally located in the second data.
12 . The memory device of claim 11 , wherein
the array of memory cells is divided into more than one planes of memory cells;
a number of the at least one process unit is equal to a number of the planes of memory cells; and
the at least one process unit corresponds to the more than one planes of memory cells one-by-one.
13 . The memory device of claim 11 , wherein
the array of memory cells is divided into more than one planes of memory cells; and
a number of the at least one process unit is less than a number of the planes of memory cells.
14 . The memory device of claim 1 , wherein the memory device comprises a NAND flash memory.
15 . A method for data calculation with a memory device comprising an array of memory cells and a peripheral circuit coupled to the memory cells, comprising:
obtaining, by a static random-access memory (SRAM), first data from a data interface of the memory device, wherein the first data is programmed into a number N of first data segments, wherein N is a positive integer and N≥2;
sensing, by page buffers of the peripheral circuit, second data from the array of memory cells, wherein the second data is programmed into the number N of data groups, each data group comprising a number M of second data segments, wherein M is a positive integer and M≥2; and
performing calculation, by at least one process unit of the peripheral circuit, based on the first and the second data.
16 . The method of claim 15 , further comprising:
programming the second data into the array of memory cells.
17 . The method of claim 16 , wherein
the first data comprises at least one row;
obtaining the first data from a data interface of the memory device comprises sending each row of the first data to the at least one process unit; and
an order of the number N of first data segments remains an original order of the first data segments located in the first data.
18 . The method of claim 17 , wherein
the second data comprises M columns;
programming the second data into the array of memory cells comprises programing each column of the second data into the memory cells; and
data lengths of the first data segments and data lengths of the second data segments are equal.
19 . The method of claim 18 , wherein performing calculation based on the first and the second data comprises:
sending, by the SRAM, the ith first data segment to each process element of the M process elements;
sending, by the page buffers, the M second data segments to the M process elements one-by-one; and
performing, by M process elements of each of the at least one process unit, convolution operations based on an ith first data segment of the N first data segments and the M second data segments of an ith data group of the N data groups.
20 . A system, comprising:
a memory device comprising:
an array of memory cells; and
a peripheral circuit coupled to the memory cells and comprising:
a static random-access memory (SRAM) configured to obtain first data transmitted from a data interface of the memory device, wherein the first data is programmed into N first data segments, wherein N is a positive integer and N≥2;
page buffers configured to sense second data from the array of memory cells, wherein the second data is programmed into N data groups, each data group comprising M second data segments, wherein M is a positive integer and M≥2; and
at least one process unit coupled to the page buffers via a data-path bus of the peripheral circuit, and configured to perform calculation based on the first data and the second data; and
a controller coupled with the memory device and configured to transmit the first data into the memory device and receive a result of the calculation from the memory device.