Processing device, network node, client device, and methods thereof
This disclosure relates to techniques for synchronization signals. The synchronization signal comprises a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with a Cell ID. The PSS sequence may be generated based on one of the first and the second sequences.
1 . A device, comprising:
a processor configured to:
generate a primary synchronization signal (PSS) sequence that carries a second index
N
ID
(
2
)
;
generate a secondary synchronization signal (SSS) sequence that carries a first index
N
ID
(
1
)
,
wherein the SSS sequence is based on a first binary sequence and a second binary sequence,
wherein the second index
N
ID
(
2
)
is encoded to a first cyclic shift m 0 of the first binary sequence, and the first index
N
ID
(
1
)
is encoded to the first cyclic shift m 0 of the first binary sequence and a second cyclic shift m 1 of the second binary sequence; and
using the SSS sequence to carry a cell identity (ID), wherein the cell ID is given by the first index
N
ID
(
1
)
and the second index
N
ID
(
2
)
.
2 . The device according to claim 1 , wherein the first index
N
ID
(
1
)
,
the second index
N
ID
(
2
)
,
the first cyclic shift m 0 , and the second cyclic shift m 1 satisfy:
m
0
=
g
(
N
ID
,
max
(
2
)
⌊
N
ID
(
1
)
L
′
⌋
+
N
ID
(
2
)
)
,
and
m
1
=
(
N
ID
(
1
)
mod
L
′
)
wherein:
g is an integer equal to or larger than 1;
L′ is a positive integer smaller than or equal to a length L of the SSS sequence;
N
ID
(
1
)
∈
{
0
,
1
,
2
,
…
,
N
ID
,
max
(
1
)
-
1
}
;
N
ID
(
2
)
∈
{
0
,
1
,
…
,
N
ID
,
max
(
2
)
-
1
}
;
└ . . . ┘ is a floor function; and
mod is a modulo operation.
3 . The device according to claim 2 , wherein the length L of the SSS sequence is 127,
N
ID
,
max
(
2
)
is
3
,
N
ID
(
2
)
∈
{
0
,
1
,
2
}
,
N
ID
,
max
(
1
)
is
336
,
and
N
ID
(
1
)
∈
{
0
,
1
,
2
,
…
,
335
}
.
4 . The device according to claim 1 , wherein the first index
N
ID
(
1
)
,
the second index
N
ID
(
2
)
,
the first cyclic shift m 0 , and the second cyclic shift m 1 satisfy:
N
ID
(
1
)
=
m
1
+
L
′
⌊
m
0
gN
ID
,
max
(
2
)
⌋
,
and
N
ID
(
2
)
=
(
m
0
g
mod
N
ID
,
max
(
2
)
)
wherein:
g is an integer equal to or larger than 1;
L′ is a positive integer smaller than or equal to a length L of the SSS sequence;
N
ID
(
1
)
∈
{
0
,
1
,
2
,
…
,
N
ID
,
max
(
1
)
-
1
}
;
N
ID
(
2
)
∈
{
0
,
1
,
…
,
N
ID
,
max
(
2
)
-
1
}
;
└ . . . ┘ is a floor function; and
mod is a modulo operation.
5 . The device according to claim 1 , wherein the processor is configured to generate the SSS sequence based on the first binary sequence cyclically shifted by the first cyclic shift m 0 and the second binary sequence cyclically shifted by the second cyclic shift m 1 , and wherein the first binary sequence, the second binary sequence, and the SSS sequence have a same length.
6 . The device according to claim 1 , wherein the first binary sequence and the second binary sequence are one in a group of:
m-sequences; or
m-sequences resulting in that generated SSS sequences belong to one set of Gold sequences, wherein the generated SSS sequences include the SSS sequence.
7 . The device according to claim 1 , wherein one of the first binary sequence or the second binary sequence utilized for generating the SSS sequence is a same binary sequence utilized for generating the PSS sequence.
8 . The device according to claim 1 , wherein a first generator polynomial of the first binary sequence meets g 0 (x)=x 7 +x 4 +1, and a second generator polynomial of the second binary sequence meets g 1 (x)=x 7 +x+1.
9 . The device according to claim 1 , wherein the SSS sequence represented as d(k) satisfies:
d
(
k
)
=
1
-
2
(
(
s
0
(
(
k
+
m
0
)
mod
L
)
+
s
1
(
(
k
+
m
1
)
mod
L
)
)
mod
2
)
,
wherein
k
∈
{
0
,
1
,
2
,
…
,
L
-
1
}
,
and
wherein
L
is a length of the
SSS
sequence
.
10 . The device according to claim 1 , wherein the cell ID is represented by
N
ID
,
wherein the first index
N
ID
(
1
)
and the second index
N
ID
(
2
)
satisfy
N
ID
=
N
ID
,
max
(
2
)
N
ID
(
1
)
+
N
ID
(
2
)
,
and wherein
N
ID
,
max
(
2
)
is a maximum number of candidate values of
N
ID
(
2
)
.
11 . The device according to claim 1 , further comprising:
a transmitter, configured to transmit a PSS based on the PSS sequence and an SSS based on the SSS sequence.
12 . A method for wireless communications, comprising:
generating a primary synchronization signal (PSS) sequence that carries a second index
N
ID
(
2
)
;
generating a secondary synchronization signal (SSS) sequence that carries a first index
N
ID
(
1
)
,
wherein the SSS sequence is based on a first binary sequence and a second binary sequence,
wherein the second index
N
ID
(
2
)
is encoded to a first cyclic shift m 0 of the first binary sequence, and the first index
N
ID
(
1
)
is encoded to the first cyclic shift m 0 of the first binary sequence and a second cyclic shift m 1 of the second binary sequence; and
using the SSS sequence to carry a cell identity (ID), wherein the cell ID is given by the first index
N
ID
(
1
)
and the second index
N
ID
(
2
)
.
13 . The method according to claim 12 , wherein the first index
N
ID
(
1
)
,
the second index
N
ID
(
2
)
,
the first cyclic shift m 0 , and the second cyclic shift m 1 satisfy:
m
0
=
g
(
N
ID
,
max
(
2
)
⌊
N
ID
(
1
)
L
′
⌋
+
N
ID
(
2
)
)
,
and
m
1
=
(
N
ID
(
1
)
mod
L
′
)
wherein:
g is an integer equal to or larger than 1;
L′ is a positive integer smaller than or equal to a length L of the SSS sequence;
N
ID
(
1
)
∈
{
0
,
1
,
2
,
…
,
N
ID
,
max
(
1
)
-
1
}
;
N
ID
(
2
)
∈
{
0
,
1
,
2
,
…
,
N
ID
,
max
(
2
)
-
1
}
;
└ . . . ┘ is a floor function; and
mod is a modulo operation.
14 . The method according to claim 13 , wherein the length L of the SSS sequence is
N
ID
,
max
(
2
)
is
3
,
N
ID
(
2
)
∈
{
0
,
1
,
2
}
,
N
ID
,
max
(
1
)
is
336
,
and
N
ID
(
1
)
∈
{
0
,
1
,
2
,
…
,
335
}
.
15 . The method according to claim 12 , wherein the first index
N
ID
(
1
)
,
the second index
N
ID
(
2
)
,
the first cyclic shift m 0 , and the second cyclic shift m 1 satisfy:
N
ID
(
1
)
=
m
1
+
L
′
⌊
m
0
g
N
ID
,
m
a
x
(
2
)
⌋
,
and
N
ID
(
2
)
=
(
m
0
g
mod
N
ID
,
m
a
x
(
2
)
)
wherein:
g is an integer equal to or larger than 1;
L′ is a positive integer smaller than or equal to a length L of the SSS sequence;
N
ID
(
1
)
∈
{
0
,
1
,
2
,
…
,
N
ID
,
m
a
x
(
1
)
-
1
}
;
N
ID
(
2
)
∈
{
0
,
1
,
…
,
N
ID
,
m
a
x
(
2
)
-
1
}
;
└ . . . ┘ is a floor function; and
mod is a modulo operation.
16 . The method according to claim 12 , wherein the SSS sequence is based on the first binary sequence cyclically shifted by the first cyclic shift m 0 and the second binary sequence cyclically shifted by the second cyclic shift m 1 , and wherein the first binary sequence, the second binary sequence, and the SSS sequence have a same length.
17 . The method according to claim 12 , wherein a first generator polynomial of the first binary sequence meets g 0 (x)=x 7 +x 4 +1, and a second generator polynomial of the second binary sequence meets g 1 (x)=x 7 +x+1.
18 . A non-transitory computer readable medium, comprising a computer program, which when executed by a computer, causes the computer to:
generate a primary synchronization signal (PSS) sequence that carries a second index
N
ID
(
2
)
and
generate a secondary synchronization signal (SSS) sequence that carries a first index
N
ID
(
1
)
wherein the SSS sequence is based on a first binary sequence and a second binary sequence,
wherein the second index
N
ID
(
2
)
is encoded to a first cyclic shift m 0 of the first binary sequence, and the first index
N
ID
(
1
)
is encoded to the first cyclic shift m 0 of the first binary sequence and a second cyclic shift m 1 of the second binary sequence; and
using the SSS sequence to carry a cell identity (ID), wherein the cell ID is given by the first index
N
ID
(
1
)
and the second index
N
ID
(
2
)
19 . The non-transitory computer readable medium according to claim 18 , wherein the first index
N
ID
(
1
)
,
the second index
N
ID
(
2
)
,
the first cyclic shift m 0 , and the second cyclic shift m 1 satisfy:
m
0
=
g
(
N
ID
,
max
(
2
)
⌊
N
ID
(
1
)
L
′
⌋
+
N
ID
(
2
)
)
,
and
m
1
=
(
N
ID
(
1
)
mod
L
′
)
wherein:
g is an integer equal to or larger than 1;
L′ is a positive integer smaller than or equal to a length L of the SSS sequence;
N
ID
(
1
)
∈
{
0
,
1
,
2
,
…
,
N
ID
,
max
(
1
)
-
1
}
;
N
ID
(
2
)
∈
{
0
,
1
,
…
,
N
ID
,
max
(
2
)
-
1
}
;
└ . . . ┘ is a floor function; and
mod is a modulo operation.
20 . The non-transitory computer readable medium according to claim 19 , wherein the length L of the SSS sequence is
N
ID
,
max
(
2
)
is
3
,
N
ID
(
2
)
∈
{
0
,
1
,
2
}
,
N
ID
,
max
(
1
)
is
336
,
and
N
ID
(
1
)
∈
{
0
,
1
,
2
,
…
,
335
}
.
21 . The method according to claim 12 , wherein the cell ID is represented by
N
ID
,
wherein the first index
N
ID
(
1
)
and the second index
N
ID
(
2
)
satisfy
N
ID
=
N
ID
,
m
ax
(
2
)
N
ID
(
1
)
+
N
ID
(
2
)
,
and wherein
N
ID
,
ma
x
(
2
)
is a maximum number of candidate values of
N
ID
(
2
)
.
22 . The non-transitory computer readable medium according to claim 18 , wherein the cell ID is represented by
N
ID
,
wherein the first index
N
ID
(
1
)
and the second index
N
ID
(
2
)
satisfy
N
ID
=
N
ID
,
m
ax
(
2
)
N
ID
(
1
)
+
N
ID
(
2
)
,
and wherein
N
ID
,
ma
x
(
2
)
is a maximum number of candidate values of
N
ID
(
2
)
.
23 . The non-transitory computer readable medium according to claim 18 , wherein the SSS sequence is based on the first binary sequence cyclically shifted by the first cyclic shift m o and the second binary sequence cyclically shifted by the second cyclic shift m 1 , and wherein the first binary sequence, the second binary sequence, and the SSS sequence have a same length.