Memory device
A memory device includes a multi-layer stack disposed on a substrate and including conductive layers and dielectric layers stacked alternately, a channel layer penetrating through the conductive layers and the dielectric layers, a charge storage layer disposed between the conductive layers and the channel layer, an insulating layer penetrating through the conductive layers and the dielectric layers and disposed between the charge storage layer and the multi-layer stack, and a first conductive pillar and a second conductive pillar enclosed by the channel layer.
1 . A memory device, comprising:
a multi-layer stack disposed on a substrate and comprising conductive layers and dielectric layers stacked alternately;
a channel layer penetrating through the conductive layers and the dielectric layers;
a charge storage layer disposed between the conductive layers and the channel layer;
an insulating layer penetrating through the conductive layers and the dielectric layers and disposed between the charge storage layer and the multi-layer stack, and a portion of the insulating layer being directly below the channel layer;
a dielectric pillar enclosed by the channel layer, wherein a sidewall of the dielectric pillar is in contact with the channel layer, the charge storage layer, and the portion of the insulating layer, and another portion of the insulating layer connected to the portion of the insulating layer continuously extends through the conductive layers and the dielectric layers; and
a first conductive pillar and a second conductive pillar penetrating through the dielectric pillar.
2 . The memory device of claim 1 , wherein the first conductive pillar and the second conductive pillar are separated from the channel layer.
3 . The memory device of claim 1 , wherein the first conductive pillar and the second conductive pillar are in contact with the channel layer.
4 . The memory device of claim 1 , further comprising:
a dielectric layer disposed between the charge storage layer and the channel layer and connected to the sidewall of the dielectric pillar.
5 . The memory device of claim 4 , wherein the insulating layer is disposed between the dielectric layer and the substrate, and between the charge storage layer and the substrate.
6 . The memory device of claim 1 , wherein the portion of the insulating layer underlies the charge storage layer and is disposed between the channel layer and the substrate.
7 . The memory device of claim 1 , wherein the sidewall of the dielectric pillar comprises a first segment interfaced with the insulating layer, a second segment interface with the charge storage layer and connected to the first segment, and a third segment interface with the channel layer and disposed above the second segment.
8 . The memory device of claim 1 , wherein the first conductive pillar is interfaced with an opposing sidewall of the dielectric pillar.
9 . The memory device of claim 1 , wherein the first conductive pillar and the second conductive pillar comprise a substantially circular top-view shape.
10 . The memory device of claim 1 , wherein the channel layer and the charge storage layer comprise a ring shape in a top view.
11 . A memory device, comprising:
a multi-layer stack disposed on a substrate and comprising word line layers and dielectric layers stacked alternately, the word line layers being elongated in a first direction;
a channel layer penetrating through the multi-layer stack, the channel layer being elongated in a second direction substantially perpendicular to the first direction;
a charge storage layer disposed between the word line layers and the channel layer, the charge storage layer being elongated in the second direction;
a first insulating layer penetrating through the multi-layer stack, the first insulating layer comprising:
a first portion extending along the second direction and between the charge storage layer and the multi-layer stack; and
a second portion connected to the first portion and extending along the first direction;
a dielectric pillar enclosed by the channel layer, a sidewall of the dielectric pillar being interfaced with the second portion of the first insulating layer, the charge storage layer, and the channel layer;
a second insulating layer disposed between the first insulating layer and the multi-layer stack, wherein the second insulating layer is in contact with a bottom surface of the dielectric pillar connected to the sidewall of the dielectric pillar, and a top surface of the second insulating layer is substantially levelled with a top surface of the dielectric pillar; and
a bit line and a source line being elongated in the second direction and separated from each other, wherein the bit line and the source line are disposed in the dielectric pillar.
12 . The memory device of claim 11 , wherein the bit line is interfaced with an opposing sidewall of the dielectric pillar.
13 . The memory device of claim 11 , wherein at least one of the bit line and the source line is in contact with the channel layer.
14 . The memory device of claim 11 , wherein the charge storage layer encircles the channel layer and is separated from the channel layer by a third insulating layer.
15 . The memory device of claim 14 , wherein the third insulating layer comprises a first portion elongated in the second direction and a second portion connected to the first portion and interfaced with the sidewall of the dielectric pillar.
16 . The memory device of claim 11 , wherein the charge storage layer comprises a first portion and a second portion connected to the first portion, the first portion of the charge storage layer extends along the first portion of the first insulating layer, and the second portion of the charge storage layer overlies and extends along the second portion of the first insulating layer, wherein the second portion of the charge storage layer is interfaced with the sidewall of the dielectric pillar.
17 . The memory device of claim 11 , wherein the second portion of the first insulating layer is disposed between the channel layer and the substrate.
18 . The memory device of claim 11 , wherein the top surface of the insulating layer is substantially levelled with a top surface of a topmost dielectric layer of the dielectric layers.
19 . A memory device, comprising:
a multi-layer stack comprising word line layers;
a channel layer penetrating through the multi-layer stack;
a charge storage layer disposed between the multi-layer stack and the channel layer;
a dielectric pillar enclosed by the channel layer, wherein the charge storage layer comprises a portion interfaced with a first segment of a sidewall of the dielectric pillar, the channel layer is interfaced with a second segment of the sidewall of the dielectric pillar above the first segment;
an insulating layer disposed between the charge storage layer and the multi-layer stack, wherein the insulating layer is in contact with a bottom surface of the dielectric pillar connected to the sidewall of the dielectric pillar, and a top surface of the insulating layer is substantially levelled with a top surface of the dielectric pillar;
a bit line pillar and a source line pillar inserted into the dielectric pillar and separated from each other, wherein lengthwise directions of the bit line pillar, the source line pillar, and the dielectric pillar are substantially perpendicular to the lengthwise direction of the multi-layer stack.
20 . The memory device of claim 19 , wherein the top surface of the insulating layer is higher than a top surface of a topmost word line layer of the word line layers.