Trench field effect transistor having improved electrical performance
A trench field effect transistor comprising a substrate. An epitaxial buffer layer is formed overlying the substrate. An epitaxial device layer is formed overlying the epitaxial buffer layer. A device body layer is formed overlying the epitaxial device layer. The substrate, epitaxial buffer layer, epitaxial device layer, and device body layer comprise silicon carbide. A trench formed in the device body layer into at least a portion of the epitaxial body layer. An insulating layer formed on the walls of the trench. A bottom of the trench is etched isotropically and forms a curved surface. The trench bottom after the isotropic etch extends past the walls of the trench and couples to the trench walls in a curve. An oxide layer is formed overlying the trench bottom and has a corresponding curve similar to the trench bottom. A gate oxide is formed on at least one wall of the trench.
1 . A trench field effect transistor (FET) comprising:
a substrate having a top surface and a bottom surface;
a patterned layer overlying the top surface of substrate comprising a plurality of trenches etched in a pattern, wherein the patterned layer further includes a layer comprising elemental carbon in the plurality of trenches; and
an epitaxial buffer layer formed on the plurality of trenches;
an epitaxial device layer overlying the epitaxial buffer layer;
a device body layer overlying the epitaxial device layer;
a trench formed through the device body layer into at least a portion of the epitaxial device layer wherein an isotropic etch is performed in the trench to etch a trench bottom in the epitaxial device layer;
an oxide layer overlying the trench bottom in the epitaxial device layer; and
a gate oxide on at least one wall of the trench.
2 . The trench FET of claim 1 wherein the substrate, the epitaxial device layer, and the device body layer comprises silicon carbide and wherein the substrate, the epitaxial buffer layer, and the device body layer are single crystal.
3 . The trench FET of claim 1 wherein the plurality of trenches forms a plurality of pillars in the patterned layer.
4 . The trench FET of claim 3 wherein the layer of elemental carbon in the plurality of trenches is less a height of the plurality of pillars.
5 . The trench FET of claim 4 wherein the epitaxial buffer layer is grown by epitaxial lateral overgrowth such that lateral growth of the epitaxial buffer layer extends from sidewalls of the plurality of trenches and merges to form the surface of the epitaxial buffer layer.
6 . The trench FET of claim 5 wherein the epitaxial device layer is grown on the surface of the epitaxial buffer layer by epitaxy.
7 . The trench FET of claim 1 wherein the substrate absorbs energy at a different wavelength than the elemental carbon.
8 . The trench FET of claim 5 wherein the plurality of trenches are shaped as hexagons or triangles.
9 . The trench FET of claim 6 1 wherein the isotropic etch is configured to form a curved surface below the wall of the trench.
10 . The trench FET of claim 9 wherein an edge of the curved surface of the trench bottom is configured to improve electrical device reliability.
11 . The trench FET of claim 10 wherein the oxide layer is configured to have a thickness in a range of 0 . 2 micrometers to 1 . 0 micrometers.
12 . The trench FET of claim 11 wherein the curvature of the oxide layer is configured to reduce an electric field to below the critical field to improve reliability of the trench FET.
13 . The trench FET of claim 12 wherein the oxide layer comprises oxide grown by wet oxidation and oxide grown by dry oxidation.
14 . The trench FET of claim 13 wherein the gate oxide overlies the oxide layer.
15 . The trench FET of claim 14 further including:
a source region formed in the device body layer;
a termination regions formed in the device body layer adjacent to the source region wherein the termination region is configured to surround or partially surround the source region.
16 . The trench FET of claim 1 wherein a plurality of trench FETs are formed overlying the substrate and wherein a dicing grid surrounds each trench FET of the plurality of trench FETs.
17 . A trench field effect transistor (FET) comprising:
a substrate having a top surface and a bottom surface wherein the substrate comprises one of silicon carbide, gallium nitride, gallium arsenide, or indium phosphide;
a patterned layer comprising a plurality of trenches etched in the top surface of the substrate, wherein a layer of material is in the plurality of trenches, wherein the material comprises elemental carbon, and wherein a height of the layer of material is less than a height of sidewalls of the patterned layer;
an epitaxial buffer layer on the patterned layer, wherein the epitaxial buffer layer is grown by epitaxial lateral overgrowth, wherein exposed portions of the sidewalls of the patterned layer supports lateral growth extending from the sidewalls of the patterned layer that merges to form a portion of a surface of the epitaxial buffer layer that is single crystal with the substrate, and wherein the surface of the epitaxial buffer layer overlies the layer of material in the patterned layer:
an epitaxial device layer overlying the patterned layer;
a device body layer overlying the epitaxial device layer;
a trench formed through the device body layer into at least a portion of the epitaxial device layer;
an oxide layer overlying the trench bottom in the epitaxial device layer wherein the oxide layer is curved corresponding to the shape of the trench bottom;
a gate oxide on at least one wall of the trench;
a source region in the device body layer; and
a gate electrode, a source electrode, and a drain electrode respectively coupled to the gate oxide, the source region, and the epitaxial device layer.
18 . The trench FET of claim 17 wherein the plurality of trenches form a plurality of pillars and wherein at least one wavelength of light is transparent to the substrate but absorbed by the elemental carbon.
19 . The trench FET of claim 18 wherein the epitaxial buffer layer supports a reduction of dislocation defects from the substrate in the epitaxial buffer layer and the device body layer.
20 . A trench field effect transistor (FET) comprising:
a substrate having a top surface and a bottom surface wherein the substrate comprises one of silicon carbide, gallium nitride, gallium arsenide, or indium phosphide;
a patterned layer overlying the substrate comprising a plurality of trenches etched in the top surface of the substrate to form a plurality of pillars, a layer of elemental carbon overlying a bottom surface of the plurality of trenches wherein the elemental carbon absorbs energy at a wavelength that is transparent to the substrate;
an epitaxial buffer layer on the patterned layer, wherein a portion of a surface of the epitaxial buffer layer comprises epitaxy overlying the layer of elemental carbon that is single crystal with the substrate;
an epitaxial device layer;
a device body layer overlying the epitaxial device layer;
a trench formed through the device body layer into at least a portion of the epitaxial device layer;
an oxide layer overlying the trench bottom in the epitaxial device layer;
a source region in the device body layer;
a gate oxide on at least one wall of the trench; and
a gate electrode, a source electrode, and a drain electrode respectively coupled to the gate oxide, the source region, and the epitaxial device layer.