Semiconductor imaging device having improved dark current performance
In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.
1 . An image sensor integrated chip, comprising:
a floating diffusion node disposed within a substrate;
a plurality of photodetectors disposed around the floating diffusion node, as viewed in a plan-view;
a plurality of transfer transistor gates disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view;
one or more transistor gates disposed on the substrate along a first side of the floating diffusion node in a plan view; and
a device isolation structure extending in a closed loop around the one or more transistor gates, wherein the device isolation structure has opposing outermost sidewalls arranged along the first side of the floating diffusion node and wherein the device isolation structure is laterally off-centered from the floating diffusion node.
2 . The image sensor integrated chip of claim 1 , further comprising:
a pick-up well region disposed within the substrate, wherein the pick-up well region is closer to the floating diffusion node than the one or more transistor gates.
3 . The image sensor integrated chip of claim 2 , wherein the pick-up well region is laterally between sidewalls of neighboring ones of the plurality of transfer transistor gates.
4 . The image sensor integrated chip of claim 2 , wherein the pick-up well region is laterally centered between two closest photodetectors of the plurality of photodetectors.
5 . The image sensor integrated chip of claim 2 , wherein a first cross-section taken between neighboring ones of the plurality of transfer transistor gates comprises the floating diffusion node and the pick-up well region.
6 . The image sensor integrated chip of claim 5 , wherein the first cross-section is completely outside of the device isolation structure.
7 . The image sensor integrated chip of claim 5 , wherein a second cross-section taken along a second direction, which is substantially perpendicular to the first cross-section, includes the pick-up well region and the one or more transistor gates.
8 . The image sensor integrated chip of claim 2 , wherein the device isolation structure extends laterally past an outermost edge of one of the plurality of photodetectors in the plan-view.
9 . An image sensor integrated chip, comprising:
a plurality of pixel regions respectively comprising:
a floating diffusion node disposed within a substrate; and
a plurality of photodetectors disposed within the substrate and around the floating diffusion node, as viewed in a plan-view; and
a plurality of device regions respectively comprising a reset gate, a source follower gate, and a select gate, the plurality of device regions comprising a first device region straddling an outer edge of a first one of the plurality of pixel regions and an outer edge of a neighboring second one of the plurality of pixel regions.
10 . The image sensor integrated chip of claim 9 , further comprising:
a pick-up well region disposed within the substrate, wherein a cross-section of the substrate that is outside of the plurality of photodetectors includes the floating diffusion node and the pick-up well region.
11 . The image sensor integrated chip of claim 9 , further comprising:
a pick-up well region disposed within the substrate, wherein the pick-up well region and the first device region are disposed along a same side of the floating diffusion node.
12 . The image sensor integrated chip of claim 11 , wherein the pick-up well region is centered on the first one of the plurality of pixel regions.
13 . The image sensor integrated chip of claim 11 , wherein the pick-up well region is substantially equal distances from two closest neighboring photodetectors of the plurality of photodetectors.
14 . The image sensor integrated chip of claim 11 , wherein the pick-up well region is separated from the floating diffusion node along a first direction in the plan-view and laterally overlaps the floating diffusion node along a second direction that is perpendicular to the first direction in the plan-view.
15 . A method for forming an image sensor integrated chip, comprising:
forming a first photodetector region in a substrate;
forming a second photodetector region in the substrate;
forming a floating diffusion node in the substrate between the first photodetector region and the second photodetector region;
forming a pick-up well contact region in the substrate, wherein the floating diffusion node and the pick-up well contact region are separated along a first direction in a plan-view and laterally overlap along a second direction that is perpendicular to the first direction in the plan-view; and
forming one or more transistor gates within a device region of the substrate, wherein the device region is laterally off-centered from the floating diffusion node along the second direction, and wherein the device region laterally straddles an outer edge of the second photodetector region.
16 . The method of claim 15 , wherein the pick-up well contact region is disposed along an end of the device region, the pick-up well contact region being further from the floating diffusion node than the device region.
17 . The method of claim 15 , wherein the floating diffusion node is formed by a first ion implantation process.
18 . The method of claim 17 , wherein the pick-up well contact region is formed by a second ion implantation process.
19 . The image sensor integrated chip of claim 1 , wherein the device isolation structure straddles opposing sides of some, but not all, of the plurality of photodetectors in the plan view.
20 . The image sensor integrated chip of claim 1 ,
wherein the one or more transistor gates are separated from one another along a first direction in the plan-view; and
wherein the device isolation structure is laterally off centered from the floating diffusion node along the first direction in the plan-view.