System control using sparse data
A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmit the sparse data pattern.
1 . A method comprising:
accessing, by a control circuit of a processor circuit, a set of data stored in a memory circuit of a computer system;
identifying, by the control circuit, a number of logical-0 bit values included within the set of data;
based on the identifying, determining, by the control circuit, that the set of data satisfies a sparseness condition;
based on the determining that the set of data satisfies the sparseness condition, compressing, by the control circuit, the set of data; and
storing, by the control circuit, the compressed set of data in the memory circuit.
2 . The method of claim 1 , wherein determining that the set of data satisfies a sparseness condition includes identifying one or more data patterns within the set of data; and
wherein storing the compressed set of data in the memory circuit includes omitting, from the compressed set of data, portions of the set of data that match one of the data patterns.
3 . The method of claim 2 , further comprising:
receiving, by the control circuit, a read command for a particular location in the memory circuit; and
based on determining that the particular location corresponds to an omitted portion of the set of data, halting access to the memory circuit for the particular location.
4 . The method of claim 3 , further comprising completing the read command by returning, by the control circuit, a default value without accessing the memory circuit.
5 . The method of claim 3 , further comprising completing the read command by returning, by the control circuit, a modified version of the omitted portion of the set of data.
6 . The method of claim 5 , wherein returning the modified version of the omitted portion of the set of data includes using an algorithm to generate a compressed version of a portion of the set of data corresponding to the sparseness condition.
7 . The method of claim 1 ,
determining, by the control circuit, that a given bank of the memory circuit has a threshold level of sparse data; and
sending, by the control circuit, a control signal to the memory circuit, wherein the control signal identifies the given bank.
8 . A system comprising:
a memory circuit and
a control circuit configured to:
access a set of data stored in the memory circuit;
determine whether ones of the set of data satisfy a sparseness condition;
based on a determination that a given data value in the set of data satisfies the sparseness condition, compress the given data value; and
storing the compressed data value in the memory circuit.
9 . The system of claim 8 , wherein to determine whether ones of the set of data satisfy the sparseness condition, the control circuit is further configured to identify ones of the set of data that correspond to a particular data pattern; and
wherein to store the compressed data value in the memory circuit, the control circuit is further configured to omit, from the compressed data value, at least a portion of bits of the given data value.
10 . The system of claim 8 , wherein the control circuit is further configured to:
receive a read command for a particular location in the memory circuit; and
based on a determination that the particular location corresponds to a compressed data value, halting access to the memory circuit for the particular location.
11 . The system of claim 10 , wherein to complete the read command, the control circuit is further configured to return a default value without accessing the memory circuit.
12 . The system of claim 10 , wherein to complete the read command, the control circuit is further configured to return a modified version of the given data value.
13 . The system of claim 12 , wherein to return the modified version of the given data value, the control circuit is further configured to generate a compressed version of the given data value.
14 . An apparatus comprising:
a memory circuit and
a control circuit configured to:
access a set of data stored in the memory circuit;
based on a number of logical-0 bit values identified within data values in the set of data, determine whether ones of the data values in the set of data satisfy a sparseness condition;
based on a determination that a particular number of data values in the set of data satisfy the sparseness condition, compress the set of data; and
store the compressed set of data in the memory circuit.
15 . The apparatus of claim 14 , wherein to determine whether ones of the data values in the set of data satisfy the sparseness condition, the control circuit is further configured to identify one or more data patterns within the set of data.
16 . The apparatus of claim 15 , wherein to store the compressed set of data in the memory circuit, the control circuit is further configured to omit, from the compressed set of data, portions of the set of data that match one of the data patterns.
17 . The apparatus of claim 16 , wherein the control circuit is further configured to:
receive a read command for a particular location in the memory circuit; and
based on a determination that the particular location corresponds to an omitted portion of the set of data, prevent access to the memory circuit for the particular location.
18 . The apparatus of claim 14 , wherein the memory circuit includes a plurality of banks; and
wherein the control circuit is further configured to track respective levels of sparse data stored in corresponding ones of the plurality of banks.
19 . The apparatus of claim 18 , wherein the control circuit is further configured to:
determine that a particular bank of the plurality of banks has a threshold level of sparse data; and
assert a control signal that identifies the particular bank.
20 . The apparatus of claim 19 , wherein the memory circuit is configured to:
receive the control signal; and
based on the control signal, reduce power to the identified bank.