Deeply integrated voltage regulator architectures
A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.
1 . A system comprising:
a substrate;
a first semiconductor die disposed on the substrate and including a load circuit, wherein the first semiconductor die further includes an error signal generation circuit;
a second semiconductor die disposed on the substrate and including a power converter circuit arranged to deliver power to the load circuit, the power converter circuit including a plurality of power switches coupled to a control circuit internal within the second semiconductor die; and
wherein the control circuit is arranged to control a power delivered to the load circuit via directly controlling the plurality of power switches; and
wherein the control circuit receives an error signal from the error signal generation circuit and in response controls a power delivered to the load circuit via the plurality of power switches.
2 . The system of claim 1 , wherein the control circuit is arranged to control the power delivered to the load circuit in response to receiving an error signal from the error signal generation circuit.
3 . The system of claim 2 , wherein the power converter circuit is coupled to the load circuit at a node and wherein the error signal represents a difference between a regulated voltage at the node and a reference voltage.
4 . The system of claim 2 , wherein the error signal is an analog voltage.
5 . The system of claim 2 , wherein the error signal is a digital signal.
6 . The system of claim 2 , wherein the error signal generation circuit comprises an analog-to-digital converter configured to generate the error signal.
7 . The system of claim 2 , wherein the power converter circuit comprises a capacitor connected to the load circuit, wherein the capacitor is integrated on the first semiconductor die.
8 . The system of claim 2 , wherein the power converter circuit comprises one or more inductors connected to the load circuit, wherein the inductors are formed on the substrate separate from the first and second semiconductor die.
9 . The system of claim 2 , wherein the plurality of power switches are integrated on the second semiconductor die.
10 . The system of claim 3 , further comprising a reference voltage generator configured to generate the reference voltage, and wherein the reference voltage generator is integrated on the first semiconductor die.
11 . The system of claim 2 , wherein the power converter circuit comprises:
a capacitor connected to the load circuit;
one or more inductors connected to the load circuit; and
wherein the plurality of power switches, the capacitor, and the one or more inductors collectively form a voltage regulator.
12 . The system of claim 11 , wherein the voltage regulator is multiphase.
13 . A method of forming a system, the method comprising:
attaching a first semiconductor die to a substrate, the first semiconductor die including a load circuit, wherein the first semiconductor die further includes an error signal generation circuit;
attaching a second semiconductor die to the substrate, the second semiconductor die including a power converter circuit arranged to deliver power to the load circuit, the power converter circuit including a plurality of power switches coupled to a control circuit internal within the second semiconductor die; and
wherein the control circuit is arranged to control a power delivered to the load circuit via directly controlling the plurality of power switches.
14 . The method of claim 13 , wherein the control circuit is arranged to control the power delivered to the load circuit in response to receiving an error signal from the error signal generation circuit.
15 . The method of claim 14 , wherein the power converter circuit is coupled to the load circuit at a node and wherein the error signal represents a difference between a regulated voltage at the node and a reference voltage.
16 . The method of claim 14 , wherein the error signal generation circuit comprises an analog-to-digital converter configured to generate the error signal.
17 . The method of claim 14 , wherein the power converter circuit comprises a capacitor connected to the load circuit, wherein the capacitor is integrated on the first semiconductor die.
18 . The method of claim 14 , wherein the power converter circuit comprises one or more inductors connected to the load circuit, wherein the inductors are formed on the substrate separate from the first and second semiconductor die.