Semiconductor structure with conductive spacer in shallow trench isolation region
A semiconductor structure includes a shallow trench isolation region disposed within a semiconductor substrate, and a conductive spacer disposed within the shallow trench isolation region.
1 . A semiconductor structure, comprising:
a shallow trench isolation region disposed within a semiconductor substrate;
a conductive spacer disposed within the shallow trench isolation region; and
a backside power rail disposed on a bottom surface of the conductive spacer;
wherein a bottom surface of the conductive spacer is coplanar with a bottom surface of the shallow trench isolation region.
2 . The semiconductor structure of claim 1 , wherein conductive spacer is disposed on a liner layer in the shallow trench isolation region.
3 . The semiconductor structure of claim 1 , wherein the conductive spacer is ruthenium.
4 . The semiconductor structure of claim 1 , further comprising a via-to-backside power rail disposed on a top surface of the conductive spacer.
5 . The semiconductor structure of claim 1 , wherein a top surface of the conductive spacer is coplanar with a top surface of the shallow trench isolation region.
6 . A semiconductor structure, comprising:
a plurality of shallow trench isolation regions disposed within a semiconductor substrate;
a conductive spacer disposed within one of the plurality of shallow trench isolation regions; and
a via-to-backside power rail disposed on a top surface of the conductive spacer;
wherein the top surface of the conductive spacer is coplanar with a top surface of the one of the plurality of shallow trench isolation regions; and
wherein the conductive spacer has a first width and the via-to-backside power rail has a second width less than the first width.
7 . The semiconductor structure of claim 6 , further comprising a liner layer disposed on sidewalls of the conductive spacer.
8 . The semiconductor structure of claim 6 , wherein a top surface of the conductive spacer is below a top surface of the one of the plurality of shallow trench isolation regions.
9 . The semiconductor structure of claim 6 , further comprising a backside power rail connected to the via-to-backside power rail though the conductive spacer.
10 . The semiconductor structure of claim 9 , wherein the backside power rail is disposed in an interlayer dielectric layer.
11 . The semiconductor structure of claim 9 , further comprising a source/drain contact disposed on the via-to-backside power rail, the source/drain contact being connected to the backside power rail through the via-to-backside power rail.
12 . The semiconductor structure of claim 6 , further comprising a gate structure, wherein the conductive spacer is located away from the gate structure.
13 . The semiconductor structure of claim 6 , wherein the conductive spacer is ruthenium.
14 . A semiconductor structure, comprising:
a plurality of shallow trench isolation regions disposed within a semiconductor substrate;
a conductive spacer disposed within one of the plurality of shallow trench isolation regions;
a plurality of stacked nanosheet channel layers located above the semiconductor substrate and between respective shallow trench isolation regions; and
a via-to-backside power rail disposed on a top surface of the conductive spacer;
wherein the top surface of the conductive spacer is coplanar with a top surface of the one of the plurality of shallow trench isolation regions; and
wherein the conductive spacer has a first width and the via-to-backside power rail has a second width less than the first width.
15 . The semiconductor structure of claim 14 , further comprising:
a source/drain region disposed on each of the plurality of stacked nanosheet channel layers; and
a source/drain contact disposed on the source/drain region and connected to the via-to-backside power rail.
16 . The semiconductor structure of claim 15 , further comprising:
a backside power rail connected to the source/drain contact though the conductive spacer and the via-to-backside power rail.
17 . The semiconductor structure of claim 16 , wherein the backside power rail is disposed on one side of the conductive spacer and the via-to-backside power rail is disposed on another side of the conductive spacer.
18 . The semiconductor structure of claim 14 , further comprising a liner layer disposed on sidewalls of the conductive spacer.
19 . The semiconductor structure of claim 17 , wherein a top surface of the conductive spacer is below a top surface of the one of the plurality of shallow trench isolation regions.
20 . The semiconductor structure of claim 14 , wherein the conductive spacer is ruthenium.