Semiconductor device
A semiconductor device may include a first active pattern and a second active pattern on a substrate, a device isolation layer in a trench between the first active pattern and the second active pattern, a first channel pattern and a second channel pattern provided on the first active pattern and the second active pattern, respectively, each of the first channel pattern and the second channel pattern including a plurality of stacked semiconductor patterns, and a gate electrode on the first channel pattern and the second channel pattern. The device isolation layer may include a first portion and a second portion which are vertically overlapped with the gate electrode. The first portion may be provided on the second portion. A silicon concentration of the first portion may be higher than a silicon concentration of the second portion.
1 . A semiconductor device, comprising:
a first active pattern and a second active pattern on a substrate;
a device isolation layer in a trench between the first active pattern and the second active pattern;
a first channel pattern and a second channel pattern provided on the first active pattern and the second active pattern, respectively, each of the first channel pattern and the second channel pattern comprising a plurality of stacked semiconductor patterns; and
a gate electrode on the first channel pattern and the second channel pattern,
wherein the device isolation layer comprises a first portion and a second portion which are vertically overlapped with the gate electrode,
the first portion is provided on the second portion, and
a silicon concentration of the first portion, extending from at least one of the first active pattern or the second active pattern, is higher than a silicon concentration of the second portion.
2 . The semiconductor device of claim 1 , wherein the silicon concentration of the first portion is in a range of about 41 atomic percent (at %) to about 45 at %.
3 . The semiconductor device of claim 2 , wherein the silicon concentration of the second portion is in a range of about 31 at % to about 35 at %.
4 . The semiconductor device of claim 1 , wherein a center region of a top surface of the first portion is flat.
5 . The semiconductor device of claim 4 , wherein an edge region of the top surface of the first portion covers side surfaces of the first and second active patterns, and the edge region has a curved shape.
6 . The semiconductor device of claim 1 , wherein the device isolation layer comprises a silicon oxide layer, a silicon oxynitride layer, or combinations thereof.
7 . The semiconductor device of claim 1 , further comprising a source/drain pattern connected to the semiconductor patterns.
8 . The semiconductor device of claim 1 , wherein the gate electrode further comprises a portion interposed between adjacent ones of the semiconductor patterns.
9 . A semiconductor device, comprising:
a first active pattern and a second active pattern on a substrate;
a device isolation layer in a trench between the first active pattern and the second active pattern;
a first channel pattern and a second channel pattern provided on the first and second active patterns, respectively, each of the first channel pattern and the second channel pattern comprising a plurality of stacked semiconductor patterns; and
a gate electrode on the first channel pattern and the second channel pattern,
wherein the device isolation layer, which is vertically overlapped with the gate electrode, comprises a first portion extending from at least one of the first active pattern or the second active pattern and having a silicon concentration in a range of about 41 at % to about 45 at %, and
a level difference between a top surface of each of the first active pattern and the second active pattern and a top surface of the first portion is larger than 0 Å and is smaller than or equal to about 200 Å.
10 . The semiconductor device of claim 9 , wherein the device isolation layer further comprises a second portion provided below the first portion, and
the silicon concentration of the first portion is higher than a silicon concentration of the second portion.
11 . The semiconductor device of claim 10 , wherein the silicon concentration of the second portion is in a range of about 31 at % to about 35 at %.
12 . The semiconductor device of claim 9 , wherein a center region of the top surface of the first portion is flat.
13 . The semiconductor device of claim 12 , wherein an edge region of the top surface of the first portion covers side surfaces of the first and second active patterns, and the edge region has a curved shape.
14 . The semiconductor device of claim 9 , wherein the device isolation layer comprises a silicon oxide layer, a silicon oxynitride layer, or combinations thereof.
15 . The semiconductor device of claim 9 , further comprising a source/drain pattern, which is provided on the active patterns and is connected to the semiconductor patterns.
16 . The semiconductor device of claim 9 , wherein the gate electrode further comprises a portion interposed between adjacent ones of the semiconductor patterns.
17 . A semiconductor device, comprising:
a substrate including an active region having active patterns thereon;
a device isolation layer between an adjacent pair of the active patterns, wherein the device isolation layer comprises a first portion and a second portion, and the first portion is on the second portion, such that the first and second portions overlap each other;
a channel pattern and a source/drain pattern on at least one of the adjacent pair of the active patterns, the channel pattern comprising a plurality of semiconductor patterns, which are vertically stacked and spaced apart from each other;
a gate electrode on the semiconductor patterns, the gate electrode comprising a portion between each adjacent pair of the plurality of semiconductor patterns;
a first gate insulating layer between each of the semiconductor patterns and the portion of the gate electrode;
a second gate insulating layer covering the at least one of the adjacent pair of the active patterns and a top surface of the device isolation layer;
a gate capping pattern on a top surface of the gate electrode;
an interlayer insulating layer on the gate capping pattern;
a gate contact provided through the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode;
a first metal layer on the interlayer insulating layer, the first metal layer comprising first interconnection lines, which are electrically connected to the gate contact, and a power line; and
a second metal layer on the first metal layer,
wherein the second metal layer comprises second interconnection lines electrically connected to the first metal layer, and
a silicon concentration of the first portion, extending from the at least one of the adjacent pair of the active patterns, of the device isolation layer is higher than a silicon concentration of the second portion.
18 . The semiconductor device of claim 17 , wherein the silicon concentration of the first portion is in a range of about 41 at % to about 45 at %.
19 . The semiconductor device of claim 18 , wherein the silicon concentration of the second portion is in a range of about 31 at % to about 35 at %.
20 . The semiconductor device of claim 17 , wherein a level difference between a top surface of the at least one of the adjacent pair of the active patterns and a top surface of the first portion is larger than 0 Å and is smaller than or equal to about 200 Å.