Backside local interconnect
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a device layer having a frontside and a backside and including a transistor that includes a source/drain region at the backside of the device layer; a first and a second backside metal line with the source/drain region at least partially overlapping vertically with the first backside metal line and not overlapping vertically with the second backside metal line; and a backside local interconnect that conductively connects the source/drain region of the transistor with the second backside metal line, where the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the source/drain region to an area outside the source/drain region of the transistor, the second portion vertically connecting the first portion to the second backside metal line. Methods for forming the same are also provided.
1 . A semiconductor structure comprising:
a device layer having a frontside and a backside, the device layer including a transistor, the transistor including a source/drain region at the backside of the device layer;
a first and a second backside metal line of a backside metal level, the source/drain region of the transistor at least partially overlapping vertically with the first backside metal line and not overlapping vertically with the second backside metal line; and
a backside local interconnect, the backside local interconnect conductively connecting the source/drain region of the transistor with the second backside metal line,
wherein the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the source/drain region of the transistor to an area outside the source/drain region of the transistor, the second portion vertically connecting the first portion to the second backside metal line.
2 . The semiconductor structure of claim 1 , wherein the source/drain region of the transistor conductively connects to the first backside metal line through a direct backside contact.
3 . The semiconductor structure of claim 1 , wherein the transistor is a first transistor, further comprising a second transistor, the second transistor having a source/drain region at the backside of the device layer, wherein the first portion of the backside local interconnect conductively connects the source/drain region of the second transistor with the source/drain region of the first transistor.
4 . The semiconductor structure of claim 3 , wherein the second backside metal line is located vertically between the first transistor and the second transistor.
5 . The semiconductor structure of claim 1 , further comprising a third backside metal line of the backside metal level, the third backside metal line being next to the second backside metal line, wherein the backside local interconnect further comprises a third portion, the third portion conductively connecting the first portion of the backside local interconnect with the third backside metal line.
6 . The semiconductor structure of claim 1 , further comprising a third backside metal line of the backside metal level, the third backside metal line being next to the first backside metal line, wherein the backside local interconnect further comprises a third portion, the third portion conductively connecting the first portion of the backside local interconnect with the third backside metal line.
7 . The semiconductor structure of claim 1 , wherein the first portion of the backside local interconnect is conductively connected to the source/drain region of the transistor through a conductive via but does not directly contact the source/drain region of the transistor.
8 . The semiconductor structure of claim 1 , wherein a first cross-section of the first portion of the backside local interconnect has a first trapezoidal shape with a top base that is narrow than a bottom base, and a second cross-section of the second portion of the backside local interconnect has a second trapezoidal shape with a top base that is wide than a bottom base, wherein the first and the second cross-section being taken in a direction orthogonal to the first and the second backside metal line.
9 . The semiconductor structure of claim 1 , wherein the source/drain region of the transistor has a width and the backside metal level has a pitch, wherein the width is smaller than the pitch.
10 . A semiconductor structure comprising:
a device layer having a frontside and a backside, the device layer including a first and a second transistor, the first transistor including a first source/drain region at the backside of the device layer, the second transistor including a second source/drain region at the backside of the device layer;
a first, a second, and a third backside metal line of a backside metal level, the first source/drain region of the first transistor at least partially overlapping vertically with the first backside metal line and does not overlapping vertically with the second backside metal line; and
a backside local interconnect, the backside local interconnect conductively connecting the first source/drain region of the first transistor with the second backside metal line,
wherein the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the first source/drain region of the first transistor to an area outside the first source/drain region of the first transistor, and the second portion vertically connecting the first portion to the second backside metal line.
11 . The semiconductor structure of claim 10 , wherein the first source/drain region of the first transistor conductively connects to the first backside metal line through a first direct backside contact.
12 . The semiconductor structure of claim 10 , wherein the first portion of the backside local interconnect conductively connects the second source/drain region of the second transistor with the first source/drain region of the first transistor.
13 . The semiconductor structure of claim 12 , wherein the second backside metal line is vertically between the first transistor and the second transistor.
14 . The semiconductor structure of claim 10 , wherein the backside local interconnect further comprises a third portion, the third portion conductively connecting the first portion of the backside local interconnect with the third backside metal line.
15 . The semiconductor structure of claim 10 , further comprising a third transistor and a fourth transistor, wherein the third transistor is vertically stacked on top of the first transistor and the fourth transistor is vertically stacked on top of the second transistor.
16 . The semiconductor structure of claim 10 , further comprising a middle-of-line (MOL) structure on top of the frontside of the device layer, and a back-end-of-line (BEOL) structure on top of the MOL structure.
17 . A method of forming a semiconductor structure comprising:
forming a device layer on top of a substrate, the device layer having a frontside and a backside and including at least one transistor, the at least one transistor including a source/drain region at the backside of the device layer;
flipping the substrate upside-down;
exposing the backside of the device layer;
forming a backside local interconnect by forming a conductive structure on top of the backside of the device layer, wherein the conductive structure includes a first portion of the backside local interconnect and a raw portion on top of the first portion, the first portion being conductively connected to the source/drain region of the at least one transistor;
etching the raw portion of the conductive structure to form a second portion of the backside local interconnect; and
forming one or more backside metal lines, one of the one or more backside metal lines being in contact with the second portion of the backside local interconnect.
18 . The method of claim 17 , wherein forming the conductive structure comprises:
depositing a dielectric layer on top of the backside of the device layer;
creating an opening in the dielectric layer, the opening exposing at least a portion of the source/drain region and an area next to the exposed portion of the source/drain region of the at least one transistor; and
filling the opening with a conductive material to form the conductive structure.
19 . The method of claim 17 , wherein forming the conductive layer comprises:
depositing a layer of conductive material on top of the backside of the device layer; and
etching the layer of conductive material to form the conductive structure in a subtractive patterning process.