Semiconductor device including diffusion break structure and method of forming semiconductor device
A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.
1 . A semiconductor device, comprising:
an insulating layer;
a first semiconductor layer over the insulating layer;
a diffusion break structure between a first active region and a second active region, the first active region including the first semiconductor layer, the diffusion break structure including a first insulating pattern over the insulating layer and an opening above the first insulating pattern; and
a conductive gate material over the opening,
wherein the first insulating pattern directly abuts the first semiconductor layer.
2 . The semiconductor device of claim 1 , further comprising a second semiconductor layer over the insulating layer, the second active region including the second semiconductor layer,
wherein the first insulating pattern directly abuts the second semiconductor layer.
3 . The semiconductor device of claim 2 , wherein the diffusion break structure further comprises a second insulating pattern between the opening and the conductive gate material.
4 . The semiconductor device of claim 3 , wherein the diffusion break structure further comprises a gate electrode material between the second insulating pattern and the conductive gate material, and
wherein the conductive gate material includes silicide, and each of the first and second insulating patterns includes silicon oxide.
5 . The semiconductor device of claim 3 , wherein the diffusion break structure further comprises a gate electrode material between the second insulating pattern and the conductive gate material.
6 . The semiconductor device of claim 2 , further comprising a spacer including a first portion over the first semiconductor layer and a second portion over the second semiconductor layer,
wherein the opening and the conductive gate material are between the first and second portions of the spacer.
7 . The semiconductor device of claim 2 , wherein the first active region, the diffusion break structure, and the second active region are arranged in a first direction, and the opening extends in the first direction, and
wherein a gate structure includes the diffusion break structure, the conductive gate material, and a hole coupled to the opening, and the gate structure extends in a second direction intersecting the first direction.
8 . The semiconductor device of claim 7 , wherein the hole is in a region of the gate structure where the gate structure extends beyond the first and second active regions.
9 . The semiconductor device of claim 7 , wherein the hole is in a region of the gate structure between the first and second active regions.
10 . The semiconductor device of claim 2 , further comprising a third semiconductor layer over the insulating layer,
wherein the diffusion break structure further includes:
a second insulating pattern over the insulating layer and abutting the second and third semiconductor layers; and
a second opening over the second insulating pattern.
11 . The semiconductor device of claim 1 , wherein the opening is a first opening, the semiconductor device further comprising a second semiconductor layer over the insulating layer,
wherein the diffusion break structure further includes:
a second insulating pattern over the insulating layer and abutting the second semiconductor layer; and
a second opening over the second insulating pattern, and
wherein the first semiconductor layer is spaced apart from the second semiconductor layer by the first insulating pattern, the first opening, the second insulating pattern, and the second opening.
12 . A semiconductor device, comprising:
an insulating layer;
a first gate structure in a first active region, the first active region including a first semiconductor layer over the insulating layer;
a second gate structure in a second active region, the second active region including a second semiconductor layer over the insulating layer; and
a third gate structure between the first and second gate structures, the third gate structure including a diffusion break structure and a conductive gate material over the diffusion break structure, the diffusion break structure including a first insulating pattern over the insulating layer and an opening over the first insulating pattern,
wherein the first insulating pattern abuts the first semiconductor layer and the second semiconductor layer, and
wherein the diffusion break structure further comprises:
a second insulating pattern disposed between the opening and the conductive gate material; and
a gate electrode material between the second insulating pattern and the conductive gate material.
13 . The semiconductor device of claim 12 , wherein the first active region, the diffusion break structure, and the second active region are arranged in a first direction,
wherein the third gate structure further includes a hole coupled to the opening, and the third gate structure extends in a second direction intersecting the first direction.
14 . The semiconductor device of claim 13 , wherein the hole is in a region of the third gate structure where the third gate structure extends beyond the first and second active regions.
15 . A method of forming a semiconductor device, the method comprising:
forming an insulating layer;
forming a first semiconductor layer over the insulating layer;
forming a diffusion break structure between a first active region and a second active region of the semiconductor device, the first active region including the first semiconductor layer; and
forming a conductive gate material,
wherein forming the diffusion break structure comprises forming an opening and a first insulating pattern under the conductive gate material, and
wherein the first insulating pattern directly abuts the first semiconductor layer.
16 . The method of claim 15 , wherein forming the diffusion break further comprises forming a second semiconductor layer over the insulating layer, the second active region including the second semiconductor layer, and
wherein the first insulating pattern directly abuts the second semiconductor layer.
17 . The method of claim 16 , wherein forming the diffusion break further comprises forming a second insulating pattern between the opening and the conductive gate material.
18 . The method of claim 15 , wherein a gate structure includes the diffusion break structure and the conductive gate material, the method further comprising forming a hole in a region of the gate structure where the gate structure extends beyond the first and second active regions.
19 . The method of claim 18 , wherein the opening is formed by applying an etchant through the hole to selectively remove a gate dielectric material in the gate structure.
20 . The method of claim 19 , wherein the first insulating pattern is formed by applying the etchant is applied through the hole to increase stress exerted on the first active region.