Packaging structure and packaging method
This disclosure relates to a packaging structure and a packaging method. The structure includes: a substrate; a first chip, including a first surface and a second surface opposite to each other; a second chip, including a third surface, where the third surface includes a third bonding region bonded to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region; a conductive post, arranged in the fourth bonding region; and a chipset, bonded to the first bonding region of the first chip, where the second bonding region is exposed from a projection of the chipset on the first chip. The chipset includes one or more third chips stacked along a longitudinal direction, adjacent third chips along the longitudinal direction are electrically connected, and the third chip adjacent to the first chip is electrically connected to the first chip.
1 . A packaging structure, comprising:
a substrate;
a first chip, comprising a first surface and a second surface opposite to each other, wherein the first surface comprises a first bonding region configured to bond to a chipset and a second bonding region configured to bond to a second chip, and the second surface is bonded to the substrate;
a second chip, comprising a third surface, wherein the third surface comprises a third bonding region bonded to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region;
a conductive post, arranged in the fourth bonding region, wherein an end of the conductive post facing away from the second chip is bonded to the substrate;
the chipset, bonded to the first bonding region of the first chip, wherein the second bonding region is exposed from a projection of the chipset on the first chip, the chipset comprises one or more third chips stacked along a longitudinal direction, adjacent third chips along a longitudinal direction are electrically connected, and the third chip adjacent to the first chip is electrically connected to the first chip; and
a first packaging layer arranged on the substrate and covering the chipset, a sidewall of the second chip, and the first chip, wherein a bottom surface of the first packaging layer is leveled with the second surface of the first chip and higher than a top surface of the substrate.
2 . The packaging structure according to claim 1 , wherein the second bonding region is arranged opposite to the third bonding region, and the packaging structure further comprises first conductive bumps arranged between the second bonding region and the third bonding region.
3 . The packaging structure according to claim 2 , further comprising:
a first sealing layer arranged between the second bonding region and the third bonding region and configured to fill a gap between the first conductive bumps and fill a region defined by the fourth bonding region and the conductive post.
4 . The packaging structure according to claim 1 , further comprising second conductive bumps arranged between the substrate and the second surface of the first chip, and between the substrate and the end of the conductive post facing away from the second chip.
5 . The packaging structure according to claim 4 , further comprising:
a first packaging layer, arranged on the substrate and covering the chipset, a sidewall of the second chip, and the first chip; and
a second sealing layer, arranged in a gap between adjacent second conductive bumps between the second surface and the substrate and in a gap between adjacent second conductive bumps between a bottom surface of the first packaging layer and the substrate.
6 . The packaging structure according to claim 1 , further comprising:
third conductive bumps arranged between the first bonding region of the first chip and the chipset.
7 . The packaging structure according to claim 1 , further comprising:
fourth conductive bumps arranged on a surface on a side of the substrate facing away from the first chip.
8 . The packaging structure according to claim 1 , wherein a ratio of an area of the second bonding region to a total area of the first chip ranges from 5% to 20%.
9 . The packaging structure according to claim 1 , wherein the first chip is a first logic chip, the second chip is a second logic chip, and the third chip is a memory chip.
10 . The packaging structure according to claim 1 , further comprising:
a thermally conductive layer, arranged on the chipset and on the second chip; and
a packaging housing, arranged on the substrate, configured to package the chipset, the second chip, and the first chip, and in contact with the thermally conductive layer.