IP Library › Granted Patent US 12,635,193
Granted Patent B2
US 12,635,193 · App. 17/751,367 · Granted May 19, 2026

Semiconductor device and method of forming same

Inventors: Hsuan-Hsiao Yao (Hsinchu, TW); Po-Kai Hsiao (Yuanlin City, TW); Fan-Cheng Lin (Hsinchu, TW); Tsai-Yu Huang (Taoyuan City, TW); Huicheng Chang (Tainan City, TW); Yee-Chia Yeo (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10D62/118H10D30/031H10D30/6713H10D30/6735H10D30/6757H10D64/017H10D84/0128H10D84/013H10D84/0158H10D84/038
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Quick Facts
Patent No.
US 12,635,193
App. No.
17/751,367
Granted
May 19, 2026
Kind
B2
Abstract

In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.

Claims (60)

1 . A method of forming a semiconductor device, the method comprising:

forming a first oxide layer over a semiconductor fin structure;

performing a first nitridation process to convert the first oxide layer to an oxynitride layer;

depositing a germanium-containing layer over the oxynitride layer;

performing a first anneal on the germanium-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and

forming a dummy gate structure over the germanium-containing layer.

2 . The method of claim 1 , wherein after performing the first anneal the oxynitride layer comprises germanium.

3 . The method of claim 1 , wherein performing the first nitridation process comprises a thermal nitridation performed at temperatures ranging from 700° C. to 1200° C. in an ambient of at least one of NH 3 , NO, N 2 O, or NO 2 .

4 . The method of claim 1 further comprising:

etching the semiconductor fin structure to form a first recess, a sidewall of the first recess exposing a semiconductor layer and a sacrificial layer of the semiconductor fin structure;

etching the sacrificial layer to form a second recess in the sidewall of the first recess; and

performing a second nitridation treatment to form a nitrogen-containing layer in the first recess and in the second recess.

5 . The method of claim 4 further comprising:

forming a dielectric layer over the nitrogen-containing layer in the first recess and in the second recess;

etching the nitrogen-containing layer and the dielectric layer, wherein after the etching the nitrogen-containing layer and the dielectric layer, remaining portions of the dielectric layer form an inner spacer in the second recess; and

epitaxially growing a source/drain region in the first recess.

6 . The method of claim 5 , wherein the source/drain region comprises germanium, and wherein after the epitaxially growing the source/drain region, the nitrogen-containing layer comprises germanium.

7 . The method of claim 6 , wherein the second nitridation treatment comprises a plasma nitridation performed at a temperature of 20° C. to 700° C. using precursors comprising at least one of N 2 , NH 3 , NO, N 2 O, and NO 2 .

8 . A method of forming a semiconductor device, the method comprising:

forming a fin structure over a substrate, the fin structure comprising a fin and nanostructures disposed over the fin, the nanostructures comprising a sacrificial layer disposed over the fin and a semiconductor layer over the sacrificial layer;

etching a first recess in the fin structure to expose a sidewall of the nanostructures;

forming a nitrogen-containing layer over a sidewall of the semiconductor layer, and a sidewall of the sacrificial layer;

forming a dielectric layer over the nitrogen-containing layer;

etching the dielectric layer and the nitrogen-containing layer to expose the sidewall of the semiconductor layer;

forming an epitaxial region in the first recess and directly adjacent to the semiconductor layer; and

performing a first anneal on the epitaxial region, wherein after the performing the first anneal, the dielectric layer comprises germanium.

9 . The method of claim 8 further comprising, prior to forming the nitrogen-containing layer, etching the sacrificial layer to form a second recess in the sidewall of the nanostructures, wherein a portion of the nitrogen-containing layer is formed in the second recess, and wherein a portion of the dielectric layer is formed in the second recess.

10 . The method of claim 8 further comprising:

removing the sacrificial layer to form a third recess interposed between the substrate and the semiconductor layer, wherein the removing the sacrificial layer comprises etching a portion of the nitrogen-containing layer; and

forming a gate electrode in the third recess.

11 . The method of claim 8 further comprising, before etching the first recess:

forming an additional nitrogen-containing layer over the fin structure;

forming a germanium-containing layer over the additional nitrogen-containing layer; and

forming a dummy gate structure over the fin structure.

12 . The method of claim 11 further comprising, after forming the germanium-containing layer and before etching the first recess in the fin, performing a second anneal, wherein after performing the second anneal the additional nitrogen-containing layer comprises germanium.

13 . The method of claim 11 further comprising:

removing the dummy gate structure;

removing the additional nitrogen-containing layer from the fin structure; and

forming a replacement gate.

14 . A method of forming a semiconductor device, the method comprising:

forming a first oxide layer over first sidewalls of a semiconductor fin structure;

performing a first nitridation process to convert the first oxide layer to an oxynitride layer;

depositing a germanium-containing layer over the oxynitride layer;

performing a first anneal on the germanium-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer;

forming a dummy gate structure over the germanium-containing layer;

etching the semiconductor fin structure to form a source/drain recess; and

forming a source/drain region in the source/drain recess.

15 . The method of claim 14 , further comprising, before etching the semiconductor fin structure to form the source/drain recess:

depositing a first gate spacer layer over the oxynitride layer; and

etching the first gate spacer layer and the oxynitride layer to expose an upper surface of the semiconductor fin structure.

16 . The method of claim 14 , further comprising, before forming the source/drain region:

forming a first dielectric layer over second sidewalls of the semiconductor fin structure in the source/drain recess, an exposed surface of the first dielectric layer being a nitride;

forming a second dielectric layer over the first dielectric layer; and

etching the second dielectric layer and the first dielectric layer to expose a portion of the second sidewalls of the semiconductor fin structure.

17 . The method of claim 16 , wherein the first nitridation process comprises a thermal nitridation performed at temperatures ranging from 700° C. to 1200° C.

18 . The method of claim 17 , wherein the thermal nitridation comprises an ambient of at least one of NH 3 , NO, N 2 O, or NO 2 .

19 . The method of claim 16 , wherein forming the second dielectric layer comprises:

forming a second oxide layer; and

performing a second nitridation process on the second oxide layer.

20 . The method of claim 19 , wherein the second nitridation process comprises a plasma nitridation performed at temperatures ranging from room temperature to 700° C.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2022
From: YAO, HSUAN-HSIAO; HSIAO, PO-KAI; LIN, FAN-CHENG; HUANG, TSAI-YU; CHANG, HUICHENG; YEO, YEE-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060332/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2022
From: YAO, HSUAN-HSIAO; PO-KAI, HSIAO; LIN, FAN-CHENG; HUANG, TSAI-YU; CHANG, HUICHENG; YEO, YEE-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060153/0133 →
Continuity (1)
Related Publication 20230378261A1 · Nov 23, 2023
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