Semiconductor device including power mesh
A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.
1 . A semiconductor device, comprising:
a base having a first surface;
source and drain electrodes and gate electrodes arranged on the first surface of the base, wherein the gate electrodes are extended along a first direction, wherein the source and drain electrodes are arranged in an array, and each of the source and drain electrodes in a row in a second direction has a first edge and a second edge opposite the first edge, wherein each first edge of the source and drain electrodes are aligned with each other, and wherein each second edge of the source and drain electrodes are aligned with each other;
a power mesh arranged below the first surface of the base, the power mesh comprising first power rails and second power rails, wherein the first power rails extend along a second direction and are separated from each other in the first direction, and the second power rails extend along the first direction and are separated from each other in the second direction; and
first vias for coupling the first power rails to the second power rails in a third direction substantially perpendicular to the first surface of the base, wherein the first vias are disposed between the first power rails and the second power rails,
wherein the first vias are aligned with crossings of the first power rails and the second power rails in the third direction.
2 . The semiconductor device of claim 1 , further comprising second vias through the base for coupling the source and drain electrodes to the power mesh in the third direction.
3 . The semiconductor device of claim 1 , further comprising signal tracks arranged above the first surface of the base and second vias for coupling the source and drain electrodes to the signal tracks in the third direction.
4 . The semiconductor device of claim 3 , wherein at least two of the second vias are arranged in rows along the second direction.
5 . The semiconductor device of claim 1 , further comprising signal tracks arranged above the first surface of the base and second vias for coupling the gate electrodes to the signal tracks.
6 . The semiconductor device of claim 5 , wherein the second vias are arranged on gate electrodes in row along the second direction.
7 . The semiconductor device of claim 1 , wherein the first direction and the second direction are substantially perpendicular to each other.
8 . The semiconductor device of claim 1 , wherein the power mesh further comprises third power rails further away from the first surface of the base than the second power rails.
9 . The semiconductor device of claim 8 , further comprising second vias through the base for coupling the second power rails to the third power rails in the third direction, wherein the second vias are aligned with crossings of the second power rails and the third power rails in the third direction.
10 . The semiconductor device of claim 1 , further comprising signal tracks arranged above the first surface of the base, wherein each of the signal tracks couples two gate electrodes adjacent and aligned in the first direction with two second vias aligned in the first direction.
11 . The semiconductor device of claim 10 , wherein the second vias corresponding to adjacent signal tracks are arranged in rows along the second direction.
12 . The semiconductor device of claim 1 , wherein the base comprises more than one substrate, and wherein source and drain electrodes and gate electrodes arranged on a first surface of a first substrate, and wherein the first power rails are arranged on a second surface of the first substrate opposite the first surface of the first substrate.
13 . The semiconductor device of claim 1 , wherein the base is a single substrate, wherein the second power rails are arranged on a second surface of the base.
14 . The semiconductor device of claim 1 , wherein the power mesh comprises more than three layers power rails, and the power rails electrically connect to the source and drain electrodes with second vias through the base.
15 . A semiconductor device, comprising:
a base having a first surface;
source and drain electrodes and gate electrodes arranged on the first surface of the base, wherein the source and drain electrodes are arranged in an array, and each of the source and drain electrodes has a first edge and a second edge opposite the first edge, wherein each first edge of the source and drain electrodes are aligned with each other, and wherein each second edge of the source and drain electrodes are aligned with each other,
a power mesh comprising first power rails and second power rails, wherein the first power rails are separated from each other in a first direction and extend along a second direction, the second power rails are separated from each other in the second direction and extend along the first direction, and the power mesh is arranged below the base; and
first vias through the base for coupling the first power rails to the second power rails,
wherein the first vias are aligned with crossings of the first power rails and the second power rails in a third direction substantially perpendicular to the first surface of the base.
16 . The semiconductor device of claim 15 , further comprising signal tracks arranged above the first surface of the base and second vias for coupling the source and drain electrodes to the signal tracks, wherein at least two of the second vias are arranged in row along the second direction.
17 . The semiconductor device of claim 15 , further comprising signal tracks arranged above the first surface of the base and second vias for coupling the gate electrodes to the signal tracks, wherein the second vias are arranged on gate electrodes in row in the second direction.
18 . A semiconductor device, comprising:
a base;
source and drain electrodes and gate electrodes on the base, wherein each of the gate electrodes has a first longitudinal section extending in a first direction;
signal tracks extended along the first direction; and
a power mesh comprising first power rails, second power rails, and third power rails, wherein the third power rails are positioned away from the first surface of the base than the second power rails, and the first power rails extend in a second direction and are separated from each other in the first direction, and the second power rails extend in the first direction and are separated from each other in the second direction, wherein the second direction is substantially perpendicular to the first direction, and
wherein the signal tracks and the power mesh are arranged at different height levels.
19 . The semiconductor device of claim 18 , further comprising first vias through the base for coupling the first power rails to the second power rails in a third direction substantially perpendicular to a first surface of the base, wherein the first vias are aligned with crossings of the first power rails and the second power rails in the third direction.
20 . The semiconductor device of claim 15 , wherein the power mesh further comprises third power rails further away from the first surface of the base than the second power rails.