Leakage compensation circuit
Circuits and methods that compensate for the problems created by low-dropout regulator (LDO) leakage current, particularly when stressed. Embodiments include an improved LDO configured to provide a load current, and which includes a leakage current compensation circuit. The leakage current compensation circuit generates a compensating current that offsets the leakage current through the pass device of the LDO during conditions that induce such leakage. More specifically, the leakage current compensation circuit can replicate the leakage current of the pass device of the LDO and feed a compensating current back into the LDO from a current mirror circuit while drawing zero-power during normal use, when leakage current is absent. LDO circuits that include a leakage current compensation circuit are particularly useful as voltage sources for positive or negative charge pumps, but are also quite useful in applications requiring a regulated voltage output.
1 . A leakage compensation circuit including:
(a) a replica device including a first terminal configured to be coupled to a voltage supply, a second terminal, and a control input configured to be coupled to the voltage supply, the replica device configured to be coupled in parallel with a circuit device and configured to substantially replicate the electrical characteristics of the circuit device; and
(b) a current mirror circuit, coupled to the second terminal of the replica device and configured to be coupled to a node of the circuit device, the current mirror circuit configured to receive an input leakage current from the replica device representative of a leakage current of the circuit device and to generate a reversed-direction compensating current at the node of the circuit device sufficient to counteract the leakage current of the circuit device.
2 . The leakage compensation circuit of claim 1 , wherein the replica device is scaled to have an N:1 size ratio with respect to the circuit device, and the current mirror circuit has a ratio of input leakage current to compensating current of 1:M, where N and M are positive integers.
3 . The leakage compensation circuit of claim 1 , wherein the circuit device and the replica device are P-type MOSFETs.
4 . The leakage compensation circuit of claim 3 , wherein the replica device is in a normally OFF configuration.
5 . The leakage compensation circuit of claim 1 , wherein the current mirror circuit includes an input FET coupled to the second terminal of the replica device, and an output FET configured to be coupled to the node of the circuit device, wherein the gates of the input FET and the output FET are connected.
6 . The leakage compensation circuit of claim 5 , wherein the input FET and the output FET are N-type MOSFETs.
7 . The leakage compensation circuit of claim 1 , wherein the compensating current is set to be equal to or greater than the leakage current of the circuit device minus a load current of the circuit device.
8 . The leakage compensation circuit of claim 1 , further including a voltage matching circuit coupled between the replica device and the current mirror circuit.
9 . The leakage compensation circuit of claim 1 , further including a voltage matching circuit coupled to the current mirror circuit and configured to be coupled to the node of the circuit device.
10 . The leakage compensation circuit of claim 1 , further including a first voltage matching circuit coupled between the replica device and the current mirror circuit, and a second voltage matching circuit coupled to the current mirror circuit and configured to be coupled to the node of the circuit device.
11 . A circuit including:
(a) a low-dropout regulator (LDO) having a pass transistor;
(b) a replica device including a first terminal configured to be coupled to a voltage supply, a second terminal, and a control input configured to be coupled to the voltage supply, the replica device coupled in parallel with the pass transistor and configured to substantially replicate electrical characteristics of the pass transistor of the LDO; and
(c) a current mirror circuit, coupled to the second terminal of the replica device and to a node of the pass transistor of the LDO, the current mirror circuit configured to receive an input leakage current from the replica device representative of a leakage current of the pass transistor and to generate a reversed-direction compensating current at the node of the pass transistor sufficient to counteract the leakage current of the pass transistor.
12 . The circuit of claim 11 , wherein the replica device is scaled to have an N:1 size ratio with respect to the pass transistor, and the current mirror circuit has a ratio of input leakage current to compensating current of 1:M, where N and M are positive integers.
13 . The circuit of claim 11 , wherein the pass transistor and the replica device are P-type MOSFETs.
14 . The circuit of claim 13 , wherein the replica device is in a normally OFF configuration.
15 . The circuit of claim 11 , wherein the current mirror circuit includes an input FET coupled to the second terminal of the replica device and an output FET coupled to the node of the pass transistor of the LDO, wherein the gates of the input FET and the output FET are connected.
16 . The circuit of claim 15 , wherein the input FET and the output FET are N-type MOSFETs.
17 . The circuit of claim 11 , wherein the compensating current is set to be equal to or greater than the leakage current of the pass transistor minus a load current of the LDO.
18 . The circuit of claim 11 , further including a voltage matching circuit coupled between the replica device and the current mirror circuit.
19 . The circuit of claim 11 , further including a voltage matching circuit coupled between the current mirror circuit and the node of the pass transistor.
20 . The circuit of claim 11 , further including a first voltage matching circuit coupled between the replica device and the current mirror circuit, and a second voltage matching circuit coupled between the current mirror circuit and the node of the pass transistor.