Semiconductor device and method for fabricating the same
The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.
1 . A semiconductor device, comprising:
a gate structure arranged on a substrate, wherein the gate structure comprises a gate insulating film disposed on the substrate, a first gate conductive film disposed on the gate insulating film, a second gate conductive film disposed on the first gate conductive film, and a gate mask film disposed on the second gate conductive film;
a plurality of word lines arranged apart from the gate structure;
two porous spacers arranged on and in contact with two sides of the gate structure, such that the porous spacers are in contact with sidewalls of the gate mask film, sidewalls of the second gate conductive film, sidewalls of the first gate conductive film, and sidewalls of the gate insulating film;
a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers;
a second insulating layer arranged over the first insulating layer, and
two spacers attached to outer sides of the two porous spacers, wherein the spacers are made of a same material of the porous spacers, such that the spacers forms two outer porous spacers respectively and each of the spacers is constructed to have a skeleton and a plurality of empty spaces disposed and distributed among the skeleton;
wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other,
wherein each of the porous spacers is constructed to have a skeleton and a plurality of empty spaces disposed and distributed among the skeleton; and
wherein a porosity of the porous spacers is between about 25% and about 100%.
2 . The semiconductor device of claim 1 , wherein the empty spaces are connected with each other and are filled with air, wherein the skeleton of each of the porous spacers is made of silicon oxide.
3 . The semiconductor device of claim 1 , further comprising two source/drain regions arranged on the substrate on outer sides of the porous spacers.
4 . The semiconductor device of claim 1 , wherein the porous spacers are laterally surrounded by the second insulating layer.
5 . The semiconductor device of claim 1 , wherein the word lines extending in the substrate.
6 . The semiconductor device of claim 1 , further comprising a stress region on the substrate between the word lines.
7 . The semiconductor device of claim 6 , wherein the substrate and the stress region have different lattice constants.
8 . The semiconductor device of claim 1 , further comprising:
a first isolation structure in the substrate defining a first active region, wherein the first active region includes the gate structure and; and
a second isolation structure in the substrate defining a second active region, wherein the second active region includes the word lines, wherein the first isolation structure has a first depth greater than a second depth of the second isolation structure.
9 . The semiconductor device of claim 1 , wherein each of the word lines further comprises a word line capping film over the respective word line electrode.