Semiconductor device
A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.
1 . A semiconductor device comprising:
an insulating layer disposed over a substrate;
a semiconductor channel region disposed over the insulating layer;
a first gate dielectric layer wrapping around a first part of the semiconductor channel region;
a first gate electrode disposed on the first gate dielectric layer and wrapping around the first part of the semiconductor channel region,
wherein the first gate dielectric layer includes a first portion disposed between the first gate electrode and the semiconductor channel region and a second portion disposed on one side face of the first gate electrode,
a second gate dielectric layer wrapping around a second part of the semiconductor channel region;
a second gate electrode disposed on the second gate dielectric layer and wrapping around the second part of the semiconductor channel region,
wherein the second portion of the first gate dielectric layer is disposed between the second gate electrode and the first gate electrode; and
a bottom dielectric layer disposed between the second gate electrode and the insulating layer,
wherein the second gate dielectric layer and the bottom dielectric layer are made of a same material.
2 . The semiconductor device of claim 1 , wherein no portion of the first gate dielectric layer is disposed on a side face opposite to another side face of the first gate electrode facing the second gate electrode.
3 . The semiconductor device of claim 1 , wherein a number of layers of the second gate dielectric layer is different than a number of layers of the first gate dielectric layer.
4 . The semiconductor device of claim 1 , wherein a height of the first gate electrode is smaller than a height of the second gate electrode.
5 . The semiconductor device of claim 1 , wherein the first gate dielectric layer is in contact with the second gate electrode.
6 . The semiconductor device of claim 1 , wherein the first gate dielectric layer is in contact with the bottom dielectric layer.
7 . The semiconductor device of claim 1 , wherein a thickness of the first gate dielectric layer is greater than a thickness of the bottom dielectric layer.
8 . The semiconductor device of claim 1 , wherein the second gate dielectric layer is made of a high-k dielectric material.
9 . The semiconductor device of claim 8 , wherein the second gate dielectric layer is made of an oxide or a silicate of Hf, Al, Zr, and combinations thereof.
10 . A semiconductor device comprising:
an insulating layer disposed over a substrate;
a semiconductor channel region disposed over the insulating layer;
a first gate dielectric layer wrapping around a first part of the semiconductor channel region;
a first gate electrode disposed on the first gate dielectric layer and wrapping around the first part of the semiconductor channel region,
wherein the first gate dielectric layer includes a first portion disposed between the first gate electrode and the semiconductor channel region, a second portion disposed on one side face of the first gate electrode, and a third portion disposed between first gate electrode and the insulating layer, and
the first gate dielectric layer is formed of three dielectric layers, an inner layer adjacent to the semiconductor channel region, a middle layer, and an outer layer adjacent to the first gate electrode;
a second gate dielectric layer wrapping around a second part of the semiconductor channel region; and
a second gate electrode disposed on the second gate dielectric layer and wrapping around the second part of the semiconductor channel region, and
wherein the second portion of the first gate dielectric layer is disposed between the second gate electrode and the first gate electrode.
11 . The semiconductor device of claim 10 , wherein no portion of the first gate dielectric layer is disposed on a side face opposite to another side face of the first gate electrode facing the second gate electrode.
12 . The semiconductor device of claim 10 , wherein one of the three dielectric layers includes HfO 2 or ZrO 2 .
13 . The semiconductor device of claim 10 , wherein the inner layer is made of an oxide, the middle layer is made of silicon nitride, and the outer layer is made of an oxide.
14 . The semiconductor device of claim 10 , wherein the middle layer is made of one of silicon nitride, SiON, HfO 2 , or ZrO 2 .
15 . The semiconductor device of claim 10 , wherein a number of layers of the second gate dielectric layer is different than a number of layers of the first gate dielectric layer.
16 . The semiconductor device of claim 10 , wherein a height of the first gate electrode is smaller than a height of the second gate electrode.
17 . The semiconductor device of claim 10 , wherein the first gate dielectric layer is in contact with the second gate electrode.
18 . The semiconductor device of claim 10 , wherein the second gate dielectric layer is made of a high-k dielectric material.
19 . The semiconductor device of claim 18 , wherein the second gate dielectric layer is made of an oxide or a silicate of Hf, Al, Zr, and combinations thereof.
20 . A semiconductor device comprising:
an insulating layer disposed over a substrate;
a semiconductor channel region disposed over the insulating layer;
a first gate dielectric layer wrapping around a first part of the semiconductor channel region;
a first gate electrode disposed on the first gate dielectric layer and wrapping around the first part of the semiconductor channel region,
wherein the first gate dielectric layer includes a first portion disposed between the first gate electrode and the semiconductor channel region, a second portion disposed on one side face of the first gate electrode, and a third portion disposed between the first gate electrode and the insulating layer, and
the first gate dielectric layer includes multiple dielectric layers;
a second gate dielectric layer wrapping around a second part of the semiconductor channel region;
a second gate electrode disposed on the second gate dielectric layer and wrapping around the second part of the semiconductor channel region,
wherein the second portion of the first gate dielectric layer is disposed between the second gate electrode and the first gate electrode; and
a bottom dielectric layer disposed between the second gate electrode and the insulating layer,
wherein the second gate dielectric layer and the bottom dielectric layer are made of a same material.